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C9822AYB

更新时间: 2024-11-24 21:09:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
17页 146K
描述
Processor Specific Clock Generator, CMOS, PDSO24, 0.150 INCH, SSOP-24

C9822AYB 技术参数

生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP,针数:24
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.84
JESD-30 代码:R-PDSO-G24JESD-609代码:e0
长度:8.65 mm端子数量:24
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.75 mm
表面贴装:YES技术:CMOS
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
宽度:3.9 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches:1

C9822AYB 数据手册

 浏览型号C9822AYB的Datasheet PDF文件第2页浏览型号C9822AYB的Datasheet PDF文件第3页浏览型号C9822AYB的Datasheet PDF文件第4页浏览型号C9822AYB的Datasheet PDF文件第5页浏览型号C9822AYB的Datasheet PDF文件第6页浏览型号C9822AYB的Datasheet PDF文件第7页 
C9822  
Direct Rambus III Clock Generator  
Product Description  
Preliminary  
Product Features  
High Speed Clock support - provides a 255 to  
533MHz differential clock source for Direct  
Rambus memory systems for an 1.66 GHz  
data transfer rate  
Synchronization Flexibility - provides signals to  
synchronize the clock domains of the Rambus  
Channel with an external system or processor  
clock, provided by C9801 and C9812.  
Power Management Support permits channel  
clocks to be enabled and disabled as required  
Supports Independent Channel Clocking  
24 pin 150 mil SSOP Package  
The C9822 is a Rambus compliant DRCG clock  
synchronizer. It contains a Phase Locked Loop that  
provides complimentary Rambus memory clocks.  
Included in its functionality is the control logic to  
phase and frequency synchronizing the device’s  
output clocks with the system reference clock. Power  
management logic is also provided for Mobil  
application and green PC functionality. Also included  
are separate power pins for each internal functional  
block so as to minimize interaction of these sections  
with each other and thus maximize the device  
performance.  
Supports Intel Architecture platforms  
Pin Configuration  
Block Diagram  
VddlR  
Refclk  
VddP  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
S0  
REFCLK  
PLL  
2
S1  
MULT 0:1  
3
VddO  
VssO  
Clk  
VssP  
4
Output  
Control  
Logic  
VssI  
5
CLK  
CLKB  
Phase  
Aligner  
PCLKM  
PclkM  
SynClkN  
VssC  
6
N/C  
SYNCLKN  
7
ClkB  
VssO  
VddO  
Mult0  
Mult1  
S2  
8
VddC  
9
VddlPD  
StopB  
PwrDnB  
10  
11  
12  
Test  
Logic  
S0:2  
STOPB  
Figure: 2  
Figure: 1  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA, Tel: 408-263-6300, Fax: 408-263-6571  
Rev 1.1  
9/7/1999  
Page 1 of 17  

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