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C9825BY

更新时间: 2024-01-05 20:47:10
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
18页 293K
描述
Processor Specific Clock Generator, CMOS, PDSO48, SSOP-48

C9825BY 技术参数

生命周期:Transferred零件包装代码:SSOP
包装说明:,针数:48
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.28
JESD-30 代码:R-PDSO-G48端子数量:48
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE认证状态:Not Qualified
表面贴装:YES技术:CMOS
端子形式:GULL WING端子位置:DUAL
uPs/uCs/外围集成电路类型:CLOCK GENERATOR, PROCESSOR SPECIFICBase Number Matches:1

C9825BY 数据手册

 浏览型号C9825BY的Datasheet PDF文件第2页浏览型号C9825BY的Datasheet PDF文件第3页浏览型号C9825BY的Datasheet PDF文件第4页浏览型号C9825BY的Datasheet PDF文件第5页浏览型号C9825BY的Datasheet PDF文件第6页浏览型号C9825BY的Datasheet PDF文件第7页 
+/+…when timing is critical  
C9825B  
Low EMI Clock Generator for Intel 133MHz/ 2DIMM Chipset Systems  
Preliminary  
Product Features  
Frequency Table (MHz)  
SEL  
PCI  
Designed for Intel’s 133MHz/SDRAM chipset  
2 copies of CPU Clock (CPU[0:1])  
9 copies of SDRAM Clock (SDRAM[0:8])  
6 copies of PCI Clocks  
3 copies of 3V66 Clock  
1 IOAPIC Clock, synchronous to PCI Clock  
1 REF Clock  
1 USB Clock (Non SSC)  
1 DOT Clock (Non SSC)  
IMI Spread Spectrum for best EMI reduction  
Dial-a-Frequency™ Feature  
Dial-a-dB™ Feature  
(3:0)**  
CPU  
SDRAM 3V66 /IOAPIC  
REF  
DOT USB  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
66.67  
100.00* 66.67  
33.33 14.318M 48M 48M  
33.33 14.318M 48M 48M  
33.33 14.318M 48M 48M  
33.33 14.318M 48M 48M  
41.67 14.318M 48M 48M  
35.64 14.318M 48M 48M  
37.50 14.318M 48M 48M  
40.32 14.318M 48M 48M  
44.95 14.318M 48M 48M  
41.67 14.318M 48M 48M  
100.00 100.00* 66.67  
133.33 133.33 66.67  
133.33 100.00* 66.67  
83.35  
125.02 83.35  
106.91 106.91 71.27  
150.00 150.00 75.00  
120.96 120.96 80.64  
89.90  
134.86 89.90  
125.02 125.02 83.35  
200.00 200.00 100.00 50.00 14.318M 48M 48M  
116.87 116.87 77.91  
100.00 133.33 66.67  
112.00 112.00 74.67  
166.53 166.53 83.27  
140.00 105.00 70.00  
38.96 14.318M 48M 48M  
33.33 14.318M 48M 48M  
37.33 14.318M 48M 48M  
41.63 14.318M 48M 48M  
35.00 14.318M 48M 48M  
48 Pin SSOP  
Block Diagram  
Table1  
*Will be set to 133 MHz, I2C Byte3, Bit0 is set to a Logic 1.  
XIN  
Pin Configuration  
36pF  
36pF  
300K  
VSS  
REF / Sel1  
VDD  
1
2
3
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
VDDI  
IOAPIC  
VSS  
VDDC  
CPU0  
CPU1  
VSS  
SDRAM0  
SDRAM1  
VDDS  
XOUT  
VDD  
REF / Sel1  
1
XIN  
4
XOUT  
VSS  
VDD  
3V66-0  
3V66-1  
3V66-2  
VSS  
5
6
7
8
VDDI  
IOAPIC  
S1  
apic  
cpu  
1
2
VDDC  
9
CPU(0:1)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Rin  
VDDS  
VDD  
VSS  
SCLK  
SDATA  
i2c-clk  
i2c-data  
SDRAM(0:8)  
3V66(0:2)  
sdram  
13  
3
PCI0 / Sel3  
PCI1  
SDRAM2  
SDRAM3  
SDRAM4  
SDRAM5  
VDDS  
SEL0  
PCI2  
VDD  
VSS  
PCI3  
PCI4  
PCI5  
Sel0  
VSS  
s0  
3V66  
pci  
VDD  
PCI(1:5)  
5
1
s2  
s3  
VSS  
PCI0/Sel3  
PLL1  
SDRAM6  
SDRAM7  
SDRAM8  
DOT  
USB / Sel2  
VDD  
VDD  
VDD  
DOT  
Rin  
48  
1
1
VDD  
SCLK  
SDATA  
USB/Sel2  
VSS  
i2c-clk  
i2c-data  
PLL2  
Fig.1  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.,  
MILPITAS, CA 95035, USA. TEL: 408-263-6300, FAX 408-263-6571  
http://www.imicorp.com  
Rev 1.2  
4/12/2000  
Page 1 of 18  

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