C9835
Low-EMI Clock Generator for Intel®
Mobile 133-MHz/3 SO-DIMM Chipset Systems
• Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and
AGP memory
Features
• Meets Intel’s Mobile 133.3MHz Chipset
• One selectable frequency for VCH video channel clock
(48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)
• Power management using power-down, CPU stop, and
PCI stop pins
• Three function select pins (include test-mode select)
• Cypress Spread Spectrum for best electromagnetic
interference (EMI) reduction
• Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)
• Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)
• Seven PCI Clocks (33MHz, 3.3V), one free running
• Two IOAPIC clocks, synchronous to CPU clock (33.3
MHz, 2.5V)
• One REF Clock
• Two 48-MHz fixed non-SSCG clocks (USB and DOT)
• SMBUS support with readback
• 56-pin SSOP and TSSOP packages
Table 1. Function Table[1]
SDRAM(0:5)
TEST#
SEL1
SEL0
CPU(0:2)
3V66(0:2)
PCIF(1:6) 48M(0:1)
REF
IOAPIC(0:10)
DCLK
0
0
1
1
1
1
X
X
0
0
1
1
0
1
0
1
0
1
Hi-Z
TCLK/2
66.6
Hi-Z
Hi-Z
TCLK/3
66.6
Hi-Z
TCLK/6
33.3
Hi-Z
TCLK/2
48
Hi-Z
Hi-Z
TCLK/6
33.3
TCLK/2
100.0[2]
100.0[2]
133.3
TCLK
14.318
14.318
14.318
14.318
100.0
133.3
133.3
66.6
33.3
48
33.3
66.6
33.3
48
33.3
100.0[2]
66.6
33.3
48
33.3
Note:
1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices
SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies.
2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.
Pin Configuration
Block Diagram
56
REF
VDD
XIN
XOUT
VSS
VSS
1
2
3
4
5
6
7
8
VSS
X IN
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2
VSS
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
DCLK
VDDS
VCH_CLK
VDD
CPU_STP#
TEST#
PD#
55
54
53
52
51
50
49
3 6 p F
3 6 p F
X O U T
V D D
R E F
1
1
V D D
3V66_0
3V66_1
3V66_2(AGP)
VDD
V C H _ C L K
V D D I
9
48
47
46
45
IO A P IC (0 ,1 )
C P U (0 :2 )
IO A P IC
C P U
2
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PCI_STP#
PCI_F
PCI1
V D D C
V D D S
C
9
8
3
5
3
44
43
42
41
R in
VSS
PCI2
PCI3
VDDP
PCI4
PCI5
PCI6
VSS
AVDD
AVSS
T E S T #
S E L 0 ,1
S D R A M ( 0 :5 )
tris ta te
s 0
S D R A M
3 V 6 6
6
3
V D D
40
39
38
37
36
35
34
33
P D #
3 V 6 6 (0 :2 )
P C I_ F
V D D P
V D D P
V D D
P C I_ S T P #
C P U _ S T P #
i2 c -c lk
i2 c -d a ta
P C I(1 :6 )
P C I
6
2
1
P L L 1
R in
4 8 M (0 ,1 )
D C L K
4 8
VSS
48M0(USB)
48M1(DOT)
VDD
24
25
26
27
V D D S
P D #
S C L K
32
31
30
P D #
SCLK
SDATA
i2 c -c lk
i2 c -d a ta
S D A T A
SEL0
28
SEL1
29
P L L 2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07303 Rev. **
Revised April 5, 2002