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C9817AYB

更新时间： 2024-01-02 04:46:25
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 光电二极管外围集成电路
页数 文件大小 规格书
19页 207K
描述
Processor Specific Clock Generator, CMOS, PDSO56, SSOP-56

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中文翻译

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C9817AYB 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：56
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.84
JESD-30 代码：R-PDSO-G56JESD-609代码：e0
长度：18.415 mm端子数量：56
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：2.794 mm
表面贴装：YES技术：CMOS
端子面层：TIN LEAD端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
宽度：7.5 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：1

C9817AYB 数据手册

 浏览型号C9817AYB的Datasheet PDF文件第7页浏览型号C9817AYB的Datasheet PDF文件第8页浏览型号C9817AYB的Datasheet PDF文件第9页浏览型号C9817AYB的Datasheet PDF文件第11页浏览型号C9817AYB的Datasheet PDF文件第12页浏览型号C9817AYB的Datasheet PDF文件第13页 
+/+…when timing is critical  
C9817  
133 MHz I2C Clock Generator for mobile Pentium®III / Rambus Systems  
Preliminary  
Frequency Extension  
Frequency Extension is a feature in this device that allows the user to expand on the clock frequency originally selected  
following table 1, page1.  
This feature provides the user two additional selection lines FS1 and FS0 that are used to select the desired percentage  
of frequency extension.  
These signals are bi-directional strapping pins and are latched into the device at power up, as described on page 3.  
This feature does not effect the frequency of the 48MHz and REF(0:2) clocks, therefore, 48MHz and REF(0:2)  
frequencies remain the same regardless of the status of FE(0:1) and Sel133/100#.  
For default frequencies (100MHz or 133.3MHz) these signals should be connect high through a 10KΩ resistor.  
When the frequency extension is applied Spread Spectrum is not applicable.  
Frequency Extension Table (MHz)  
Sel133/100# FE1  
FE0  
CPU  
CPU/2  
3V66(0:2) PCI(F,0:6) IOAPIC(0:1)  
Function  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
120  
110  
105  
100  
160  
146.67  
140  
133.3  
60  
55  
52.5  
50  
80  
73.33  
70  
80  
73.33  
70  
66.6  
80  
40  
36.67  
35  
33.3  
40  
36.67  
35  
33.3  
20  
20 % extension to 100 MHz  
10 % extension to 100 MHz  
5 % extension to 100 MHz  
0 %, DEFAULT, 100 MHz  
20 % extension to 133.3  
10 % extension to 133.3  
5 % extension to 133.3 MHz  
0 %, DEFAULT, 133.3 MHz  
18.33  
17.5  
16.67  
20  
18.33  
17.5  
16.67  
73.33  
70  
66.6  
66.6  
Table 5.  
Maximum Ratings  
This device contains circuitry to protect the inputs  
against damage due to high static voltages or electric  
field; however, precautions should be taken to avoid  
application of any voltage higher than the maximum  
rated voltages to this circuit. For proper operation, Vin  
and Vout should be constrained to the range:  
Maximum Input Voltage Relative to VSS: VSS - 0.3V  
Maximum Input Voltage Relative to VDD: VDD + 0.3V  
Storage Temperature:  
Operating Temperature:  
Maximum ESD protection  
Maximum Power Supply:  
-65ºC to + 150ºC  
0ºC to +85ºC  
2000V  
5.5V  
VSS<(Vin or Vout)<VDD  
Unused inputs must always be tied to an appropriate  
logic voltage level (either VSS or VDD).  
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.  
MILPITAS, CA 95035 TEL: 408-263-6300 FAX 408-263-6571  
WWW.IMICORP.COM  
Rev 1.0  
11/1/1999  
Page 10 of 19  
1...78910111213...19

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