Datasheet > BSP3505D

BSP3505D

更新时间： 2024-01-30 02:59:14

品牌	Logo	应用领域
MICRONAS		/
页数	文件大小	规格书
40页	264K
描述
Baseband Sound Processor

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BSP3505D 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	QFP,	针数：	80
Reach Compliance Code：	unknown	风险等级：	5.63
商用集成电路类型：	VOLUME CONTROL CIRCUIT	JESD-30 代码：	R-PQFP-G80
长度：	20 mm	端子数量：	80
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK
认证状态：	Not Qualified	座面最大高度：	3.2 mm
表面贴装：	YES	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

BSP3505D 数据手册

BSP 3505D

PRELIMINARY DATA SHEET

3. I C Bus Interface: Device and Subaddresses

Due to the internal architecture of the BSP 3505D the IC

cannot react immediately to an I C request. The typical

Asaslavereceiver, theBSP3505Dcanbecontrolledvia

I C bus. Access to internal memory locations is

achieved by subaddressing. The DSP processor part

has its own subaddressing register bank.

response time is about 0.3 ms for the DSP processor

part. If the receiver (BSP) can’t receive another com-

plete byte of data until it has performed some other func-

tion; for example, servicing an internal interrupt, it can

hold the clock line I C_CL LOW to force the transmitter

In order to allow for more BSP or MSP ICs to be con-

nected to the control bus, an ADR_SEL pin has been im-

plemented. With ADR_SEL pulled to high, low, or left

open, the BSP 3505D responds to changed device ad-

dresses. Thus, three identical devices can be selected.

into a wait state. The positions within a transmission

where this may happen are indicated by ’Wait’ in section

3.1. ThemaximumWait-periodoftheBSPduringnormal

operation mode is less than 1 ms.

I C-Bus conditions caused by BSP hardware problems:

By means of the RESET bit in the CONTROL register,

all devices with the same device address are reset.

In case of any internal error, the BSPs wait-period is ex-

tended to 1.8 ms. Afterwards, the BSP does not ac-

knowledge (NAK) the device address. The data line will

be left HIGH by the BSP and the clock line will be re-

leased. The master can then generate a STOPcondition

to abort the transfer.

The IC is selected by asserting a special device address

in the address part of an I C transmission. A device ad-

dress pair is defined as a write address (80, 84, or 88

)

hex

and a read address (81, 85, or 89 ). Writing is done by

hex

sending the device write address first, followed by the

subaddress byte, two address bytes, and two data by-

tes. Reading is done by sending the device write ad-

dress, followed by the subaddress byte and two address

bytes. Without sending a stop condition, reading of the

addresseddataiscompletedbysendingthedeviceread

By means of NAK, the master is able to recognize the er-

ror state and to reset the IC via I C-Bus. While transmit-

ting the reset protocol (s. 5.2.4.) to ‘CONTROL’, the

master must ignore the not acknowledge bits (NAK) of

the BSP.

address (81, 85, or 89 ) and reading two bytes of data.

A general timing diagram of the I C Bus is shown in

hex

Fig. 3–2.

Refer to Fig. 3–1: I C Bus Protocol and section 3.2. Pro-

posal for BSP 3505D I C Telegrams.

Table 3–1: I C Bus Device Addresses

ADR_SEL

Low

High

Left Open

Read

Mode

Write

Read

Write

Read

Write

BSP device address

hex

Table 3–2: I C Bus Subaddresses

Name

Binary Value

Hex Value

Mode

Function

CONTROL

TEST

0000 0000

0000 0001

0001 0010

0001 0011

Write

software reset

only for internal use

write address DSP

read address DSP

WR_DSP

RD_DSP

Micronas

1...4 5 678 9 10...40

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