Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BSI
BS616LV8021
DESCRIPTION
FEATURES
The BS616LV8021 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from
a wide range of 2.7V to 3.6V supply voltage.
• Very low operation voltage : 2.7 ~ 3.6V
• Very low power consumption :
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
1uA (Typ.) CMOS standby current
• High speed access time :
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
-70
70ns (Max.) at Vcc=3.0V
-10 100ns (Max.) at Vcc=3.0V
•Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV8021 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
The BS616LV8021 is available in 48-pin BGA type.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
(ns)
(ICCSB1, Max)
(ICC, Max)
PKG TYPE
TEMPERATURE
RANGE
Vcc=3.0V
Vcc=3.0V
16uA
Vcc=3.0V
20mA
BS616LV8021AC
BS616LV8021AI
+0 O C to +70 O
-40 O C to +85 O
C
C
2.7V ~ 3.6V
2.7V ~ 3.6V
70 / 100
70 / 100
BGA-48-0608
BGA-48-0608
24uA
25mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
A15
A14
A13
1
2
3
4
5
6
A12
A11
A10
A9
Address
Input
A
B
C
D
E
F
CE2
LB
OE
A0
A1
A2
22
2048
Row
Decoder
Memory Array
2048 x 4096
Buffer
D8
D9
UB
D10
D11
A3
A5
A4
A6
CE1
D1
D0
D2
A8
A17
A7
A6
4096
Data
16(8)
16(8)
Column I/O
Input
D0
A17
A7
D3
D4
D5
Buffer
VSS
VCC
VSS
D6
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
256(512)
Data
A16
A 15
A13
A10
VCC D12
VSS
A14
A12
A9
Output
Buffer
Column Decoder
D15
D14
D15
A18
D13
CI.O
A8
CE1
CE2
WE
OE
UB
16(18)
Control
Address Input Buffer
G
H
D7
WE
LB
CIO
A16 A0 A1 A2 A3 A4
A5 A18
(SAE)
A11 SAE.
Vdd
Vss
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.3
April 2002
R0201-BS616LV8021
1