Very Low Power/Voltage CMOS SRAM
512K x 16 or 1M x 8 bit switchable
BSI
BS616LV8022
FEATURES
DESCRIPTION
• Very low operation voltage : 2.4 ~ 5.5V
• Very low power consumption :
The BS616LV8022 is a high performance, very low power CMOS Static
Random Access Memory organized as 524,288 words by 16 bits or
1,048,576 bytes by 8 bits selectable by CIO pin and operates from a wide
range of 2.4V to 5.5V supply voltage.
Vcc = 3.0V C-grade: 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.5uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 45mA (Max.) operating current
I-grade : 50mA (Max.) operating current
3uA (Typ.) CMOS standby current
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 0.5uA and maximum access time of 70/100ns in 3.0V operation.
Easy memory expansion is provided by an active HIGH chip
enable2(CE2), active LOW chip enable1(CE1), active LOW output
enable(OE) and three-state output drivers.
• High speed access time :
-70
70ns (Max.) at Vcc= 3.0V
-10 100ns (Max.) at Vcc= 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616LV8022 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616LV8022 is available in 48-pin BGA type.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
RANGE
Vcc=3.0V
Vcc=3V
3uA
Vcc=5V Vcc=3V Vcc=5V
BS616LV8022BC +0OC to +70OC 2.4V ~ 5.5V 70 / 100
BS616LV8022BI -40OC to +85OC 2.4V ~ 5.5V 70 / 100
30uA
20mA 45mA
25mA 50mA
BGA-48-0810
BGA-48-0810
6uA
100uA
BLOCK DIAGRAM
PIN CONFIGURATIONS
A15
A14
A13
1
2
3
4
5
6
A12
A11
A10
A9
Address
Input
A
B
C
D
E
F
CE2
D0
LB
D8
OE
UB
A0
A3
A1
A4
A2
CE1
D1
22
2048
Row
Memory Array
2048 x 4096
Buffer
A8
Decoder
A17
A7
A6
D9
A5
A6
D2
D10
D11
D12
4096
Data
16(8)
16(8)
Column I/O
Input
D0
A17
A7
D3
D4
D5
Buffer
VSS
VCC
D14
VCC
VSS
D6
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
256(512)
Data
A16
A15
A13
A10
VSS
A14
A12
A9
Output
Buffer
Column Decoder
D15
D13
CE1
CE2
WE
OE
UB
16(18)
D15 CI.O
A8
D7
Control
Address Input Buffer
G
H
WE
LB
CIO
A16 A0 A1 A2 A3 A4
A5 A18
(SAE)
A18
A11 SAE.
Vdd
Vss
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.4
April 2002
R0201-BS616LV8022
1