Datasheet > BL24C02H

BL24C02H

更新时间： 2023-12-06 19:46:12

品牌	Logo	应用领域
上海贝岭 - BELLING		存储
页数	文件大小	规格书
20页	419K
描述
BL24C02F提供2048比特串行电可擦写存储器，组成256个字节，每页16个字节，共16页。

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数据手册

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BL24C02H 数据手册

BL24C02H 2K bits (256×8)

4. Write Operations

BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and

acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the

first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing

device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the

EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during

this write cycle and the EEPROM will not respond until the write is complete (see Figure 7).

Figure 6. ADDRESS

DEVICE

ADDRESS

DATA

SDA

LINE

L R A

L A

S C

B K

L A

S C

B K

/ C

B W K

Figure 7. Byte Write

PAGE WRITE: The 2K EEPROM is capable of a 8-byte page write. A page write is initiated the same as a byte

write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after

the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven more

data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must

terminate the page write sequence with a stop condition (see Figure 8).

DEVICE

ADDRESS

DATA(n)

DATA(n+1)

SDA

LINE

L R A

L A

S C

B K

L A

S C

B K

/ C

B W K

Figure 8. Page Write

The data word address lower three bits are internally incremented following the receipt of each data word. The

higher data word address bits are not incremented, retaining the memory page row location. When the word

address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the

same page. If more than eight data words are transmitted to the EEPROM, the data word address will "roll over"

and previous data will be overwritten.

ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are

disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device

address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has

completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.

BL24C02H 2K bits (256×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited

6-20

1...3 4 567 8 9...20

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