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AZ10/100EL16VOXP PDF预览

AZ10/100EL16VOXP

更新时间: 2024-11-08 06:38:51
品牌 Logo 应用领域
其他 - ETC 振荡器
页数 文件大小 规格书
18页 259K
描述
ECL/PECL Oscillator Gain Stage and Buffer with Enable

AZ10/100EL16VOXP 数据手册

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ARIZONA MICROTEK, INC.  
AZ10EL16VO  
AZ100EL16VO  
ECL/PECL Oscillator Gain Stage and Buffer with Enable  
FEATURES  
Green and RoHS Compliant Available  
250ps Propagation Delay on Q¯ Output  
High Voltage Gain vs. Standard EL16  
For Oscillator Applications  
Available in 2x2 or 3x3mm MLP Package  
75kΩ Enable Pull-Down Resistor  
S–Parameter (.s2p) and IBIS Model  
Files Available on Arizona Microtek Website  
DESCRIPTION  
The AZ10/100EL16VO is an oscillator gain stage with a high gain output buffer including an enable. The  
QHG/Q¯HG outputs have a voltage gain several times greater than the Q/Q¯ outputs. An enable input (E¯N¯ ) allows  
continuous oscillator operation. When E¯N¯ is LOW or floating (NC), input data is passed to both sets of outputs.  
When E¯N¯ is HIGH, the QHG/Q¯HG outputs will be forced LOW/HIGH respectively, while input data will continue to  
be passed to the Q/Q¯ outputs. The E¯N¯ input can be driven with an ECL/PECL signal or a CMOS logic signal.  
The input impedance of the D/D¯ inputs remain constant for all operating modes since forcing the outputs via the  
E¯N¯ pin does not power-down the chip but only disables the high gain QHG/Q¯HG outputs.  
Input protection diodes are included on the D/D¯ inputs for enhanced ESD protection.  
The EL16VO also provides a VBB output that supports 1.5mA sink/source current. When used, the VBB pin  
should be bypassed to ground or VCC via a 0.01μF capacitor.  
Any used output must have an external pull down resistor. For 3.3V operation, an 180resistor to VEE is  
recommended if an AC coupled load is present. At 5.0V, a 330resistor is recommended for the AC load case.  
Alternately, a 50load terminated to VCC – 2V or the Thevenin equivalent may be driven directly. Unused outputs  
may be left floating (NC).  
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.  
PIN/PAD DESCRIPTION  
Q
PIN  
D/D¯  
FUNCTION  
Data Inputs  
Q
Q/Q¯  
QHG/Q¯HG  
VBB  
Data Outputs  
D
D
QHG  
QHG  
Data Outputs w/High Gain  
Reference Voltage Output  
Enable Input  
E¯N¯  
VCC  
Positive Supply  
EN  
VBB  
VEE  
Negative Supply  
1630 S. STAPLEY DR., SUITE 127 MESA, ARIZONA 85204 USA (480) 962-5881 FAX (480) 890-2541  
www.azmicrotek.com  

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