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ATF1508BE-7AU100 PDF预览

ATF1508BE-7AU100

更新时间： 2024-01-08 03:33:48
品牌 Logo 应用领域
爱特美尔 - ATMEL /
页数 文件大小 规格书
30页 769K
描述
Highperformance CPLD

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中文翻译

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ATF1508BE-7AU100 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：TFQFP, TQFP100,.63SQ
针数：100Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.73其他特性：YES
最大时钟频率：210 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G100JTAG BST：YES
长度：14 mm专用输入次数：4
I/O 线路数量：80宏单元数：128
端子数量：100最高工作温度：85 °C
最低工作温度：-40 °C组织：4 DEDICATED INPUTS, 80 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
电源：1.5/3.3,1.8 V可编程逻辑类型：EE PLD
传播延迟：6 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

ATF1508BE-7AU100 数据手册

 浏览型号ATF1508BE-7AU100的Datasheet PDF文件第7页浏览型号ATF1508BE-7AU100的Datasheet PDF文件第8页浏览型号ATF1508BE-7AU100的Datasheet PDF文件第9页浏览型号ATF1508BE-7AU100的Datasheet PDF文件第11页浏览型号ATF1508BE-7AU100的Datasheet PDF文件第12页浏览型号ATF1508BE-7AU100的Datasheet PDF文件第13页 
3. Power Management  
Unlike conventional CPLDs with sense amplifiers, the ATF1508BE is designed using low-power  
full CMOS design techniques. This enables the ATF1508BE to achieve extremely low power  
consumption over the full operating frequency spectrum.  
The ATF1508BE also has an optional power-down mode. In this mode, current drops to below  
100 µA. When the power-down option is selected, either PD1 or PD2 pins (or both) can be used  
to power down the part. When enabled, the device goes into power-down when either PD1 or  
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any  
enabled outputs.  
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is  
enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However, the pin’s mac-  
rocell may still be used to generate buried foldback and cascade logic signals.  
All power-down AC characteristic parameters are computed from external input or I/O pins.  
4. Security Feature  
A fuse is provided to prevent unauthorized copying of the ATF1508BE fuse patterns. Once  
enabled, fuse reading or verification is inhibited. However, the 16-bit User Electronic Signature  
remains accessible. To reset this feature, the entire memory array in the device must be erased.  
5. Programming Methods  
The ATF1508BE devices are In-System Programmable (ISP) or In-System Configurable (ISC)  
devices utilizing the 4-pin JTAG protocol. This capability eliminates package handling normally  
required for programming and facilitates rapid design iterations and field changes.  
When using the ISP hardware or software to program the ATF1508BE devices, four I/O pins  
must be reserved for the JTAG interface. However, the logic features that the macrocells have  
associated with these I/O pins are still available to the design for buried logic functions.  
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors, Serial Vector  
Format (SVF) files can be created by Atmel-provided software utilities. ATF1508BE devices can  
also be programmed using standard third-party programmers. With a third-party programmer,  
the JTAG ISP port can be disabled, thereby allowing four additional I/O pins to be used for logic.  
The ATF1508BE device supports several configuration modes which gives designers several  
unique options for programming.  
The different modes of programming are:  
• ISC – In-System Configuration  
• OTF – On-the-Fly Reconfiguration  
• DRA – Direct Reconfiguration Access  
10  
ATF1508BE  
3663A–PLD–1/08  
1...78910111213...30

中文翻译

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ATF1508BE-7AU100 替代型号

型号 品牌 替代类型 描述 数据表
ATF1508BE-5AX100 ATMEL

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