Datasheet > ATF1508BE-7AU100

ATF1508BE-7AU100

更新时间： 2024-01-30 22:38:14

品牌	Logo	应用领域
爱特美尔 - ATMEL		/
页数	文件大小	规格书
30页	769K
描述
Highperformance CPLD

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ATF1508BE-7AU100 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
风险等级：	5.73	其他特性：	YES
最大时钟频率：	210 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100	JTAG BST：	YES
长度：	14 mm	专用输入次数：	4
I/O 线路数量：	80	宏单元数：	128
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4 DEDICATED INPUTS, 80 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
电源：	1.5/3.3,1.8 V	可编程逻辑类型：	EE PLD
传播延迟：	6 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Programmable Logic Devices
最大供电电压：	1.9 V	最小供电电压：	1.7 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

ATF1508BE-7AU100 数据手册

ATF1508BE

1.1

1.2

Product Terms and Select Mux

Each ATF1508BE macrocell has five product terms. Each product term receives as its inputs all

signals from the switch matrix and regional bus.

The product term select multiplexer (PTMUX) allocates the five product terms as needed to the

macrocell logic gates and control signals. The PTMUX configuration is determined by the design

compiler, which selects the optimum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1508BE’s logic structure is designed to efficiently support all types of logic. Within a sin-

gle macrocell, all the product terms can be routed to the OR gate, creating a 5-input AND/OR

sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to

as many as 40 product terms with minimal additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic functions.

One input to the XOR comes from the OR sum term. The other XOR input can be a product term

or a fixed high or low level. For combinatorial outputs, the fixed level input allows polarity selec-

tion. For registered functions, the fixed levels allow DeMorgan minimization of product terms.

1.3

Flip-flop

The ATF1508BE’s flip-flop has very flexible data and control functions. The data input can come

from either the XOR gate, from a separate product term or directly from the I/O pin. Selecting the

separate product term allows creation of a buried registered feedback within a combinatorial out-

put macrocell. (This feature is automatically implemented by the fitter software). In addition to D,

T, JK and SR operation, the flip-flop can also be configured as a flow-through latch. In this

mode, data passes through when the clock is high and is latched when the clock is low.

The clock itself can be any one of the Global CLK signals (GCK[0 : 2]) or an individual product

term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the

clock, one of the macrocell product terms can be selected as a clock enable. When the clock

enable function is active and the enable signal (product term) is low, all clock edges are ignored.

The flip-flop’s asynchronous reset signal (AR) can be either the Global Clear (GCLEAR), a prod-

uct term, or always off. AR can also be a logic OR of GCLEAR with a product term. The

asynchronous preset (AP) can be a product term or always off.

1.4

1.5

Extra Feedback

The ATF1508BE macrocell output can be selected as registered or combinatorial. The extra bur-

ied feedback signal can be either combinatorial or a registered signal regardless of whether the

output is combinatorial or registered. (This enhancement function is automatically implemented

by the fitter software.) Feedback of a buried combinatorial output allows the creation of a second

latch within a macrocell.

I/O Control

The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be individ-

ually configured as an input, output or bi-directional pin. The output enable for each macrocell

can be selected from the true or complement of the two output enable pins, a subset of the I/O

pins, or a subset of the I/O macrocells. This selection is automatically done by the fitter software

when the I/O is configured as an input or bi-directional pin.

3663A–PLD–1/08

1...4 5 678 9 10...30

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