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ATF1508BE-7AU100

更新时间： 2024-01-06 21:24:12

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ATF1508BE-7AU100 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TFQFP, TQFP100,.63SQ
针数：	100	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.31.00.01
风险等级：	5.73	其他特性：	YES
最大时钟频率：	210 MHz	系统内可编程：	YES
JESD-30 代码：	S-PQFP-G100	JTAG BST：	YES
长度：	14 mm	专用输入次数：	4
I/O 线路数量：	80	宏单元数：	128
端子数量：	100	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4 DEDICATED INPUTS, 80 I/O
输出函数：	MACROCELL	封装主体材料：	PLASTIC/EPOXY
封装代码：	TFQFP	封装等效代码：	TQFP100,.63SQ
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE, FINE PITCH
电源：	1.5/3.3,1.8 V	可编程逻辑类型：	EE PLD
传播延迟：	6 ns	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Programmable Logic Devices
最大供电电压：	1.9 V	最小供电电压：	1.7 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	宽度：	14 mm
Base Number Matches：	1

Each of the 128 macrocells generates a buried feedback signal that goes to the global bus (see

Figure 1-3). Each input and I/O pin also feeds into the global bus. The switch matrix in each logic

block then selects 40 individual signals from the global bus. Each macrocell also generates a

foldback logic term that goes to a regional bus. Cascade logic between macrocells in the

ATF1508BE allows fast, efficient generation of complex logic functions. The ATF1508BE con-

tains eight such logic chains, each capable of creating sum term logic with a fan-in of up to 40

product terms.

The ATF1508BE macrocell, shown in Figure 1-4, is highly flexible and capable of supporting

complex logic functions operating at high speed. The macrocell consists of five sections: product

terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop, output select

and enable, and logic array inputs.

A security fuse, when programmed, protects the contents of the ATF1508BE. Two bytes

(16 bits) of User Electronic Signature are accessible to the user for purposes such as storing

project name, part number, revision or date. The User Electronic Signature is accessible regard-

less of the state of the security fuse.

The ATF1508BE device supports In-System Programming (ISP) via the industry-standard 4-pin

JTAG interface (IEEE 1532 standard), and is fully compliant with IEEE 1149.1 for Boundary

Scan Test. ISP allows the device to be programmed without removing it from the printed circuit

board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to

be made in the field via software.

Figure 1-4. ATF1508BE Macrocell

BURIED FEEDBACK

SCHMITT

TRIGGER

SSTL

ATF1508BE

3663A–PLD–1/08

1...3 4 567 8 9...30

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