Datasheet > ATF1500A-15AU

ATF1500A-15AU

更新时间： 2024-01-20 00:36:34

品牌	Logo	应用领域
爱特美尔 - ATMEL		可编程逻辑
页数	文件大小	规格书
19页	594K
描述
EE PLD, 15ns, 32-Cell, CMOS, PQCC44

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技术参数
数据手册

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ATF1500A-15AU 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.61	其他特性：	NO
系统内可编程：	NO	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e3	JTAG BST：	NO
湿度敏感等级：	3	宏单元数：	32
端子数量：	44	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC44,.7SQ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
峰值回流温度（摄氏度）：	260	电源：	5 V
可编程逻辑类型：	EE PLD	传播延迟：	15 ns
认证状态：	Not Qualified	子类别：	Programmable Logic Devices
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	端子面层：	Matte Tin (Sn)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40

ATF1500A-15AU 数据手册

ATF1500A(L)

In addition to D, T, JK and SR operation, the flip-flop can

also be configured as a flow-through latch. In this mode,

data passes through when the clock is high and is latched

when the clock is low.

The output enable multiplexer (MOE) controls the output

enable signals. Any buffer can be permanently enabled for

simple output operation. Buffers can also be permanently

disabled to allow use of the pin as an input. In this configu-

ration all the macrocell resources are still available, includ-

ing the buried feedback, expander and CASCADE logic.

The clock itself can be either the global CLK pin or an indi-

vidual product term. The flip-flop changes state on the

clock’s rising edge. When the CLK pin is used as the clock,

one of the macrocell product terms can be selected as a

clock enable. When the clock enable function is active and

the enable signal (product term) is low, all clock edges are

ignored.

The output enable for each macrocell can also be selected

as either of the two OE pins or as an individual product

term.

Global/Regional Busses

The global bus contains all Input and I/O pin signals as well

as the buried feedback signal from all 32 macrocells.

Together with the complement of each signal, this provides

a 68-bit bus as input to every product term. Having the

entire global bus available to each macrocell eliminates

any potential routing problems. With this architecture

designs can be modified without requiring pinout changes.

The flip-flop’s asynchronous reset signal (AR) can be either

the pin global clear (GCLR), a product term, or always off.

AR can also be a logic OR of GCLR with a product term.

The asynchronous preset (AP) can be a product term or

always off.

Output Select and Enable

The ATF1500A macrocell output can be selected as regis-

tered or combinatorial. When the output is registered, the

same registered signal is fed back internally to the global

bus. When the output is combinatorial, the buried feedback

can be either the same combinatorial signal or it can be the

the flip-flop input.

Each macrocell also generates a foldback product term.

This signal goes to the regional bus, and is available to 16

macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The 16 foldback terms in each

region allow generation of high fan-in sum terms (up to 21

product terms) with little additional delay.

1 2 3 456 7 8...19

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与ATF1500A-15AU相关器件

型号	品牌	描述	获取价格	数据表
ATF1500A-15JC	ATMEL	High Performance E2 PLD	获取价格
ATF1500A-15JI	ATMEL	High Performance E2 PLD	获取价格
ATF1500A-15JJ	ATMEL	Flash PLD, 15ns, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1500A-15JL	ATMEL	Flash PLD, 15ns, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44	获取价格
ATF1500A-15JU	ATMEL	EE PLD	获取价格
ATF1500A-20AC	ATMEL	Flash PLD, 20ns, PQFP44, 10 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MS-026ACB, TQFP-	获取价格

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