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AT17LV512A-10PL PDF预览

AT17LV512A-10PL

更新时间: 2024-10-27 19:33:19
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟光电二极管内存集成电路
页数 文件大小 规格书
18页 318K
描述
Configuration Memory, 512KX1, Serial, CMOS, PDIP8, 0.300 INCH, PLASTIC, MS-001BA, DIP-8

AT17LV512A-10PL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.77其他特性:ALSO OPERATES AT 5V SUPPLY
最大时钟频率 (fCLK):15 MHzJESD-30 代码:R-PDIP-T8
JESD-609代码:e3长度:9.271 mm
内存密度:524288 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:1
功能数量:1端子数量:8
字数:524288 words字数代码:512000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX1
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装形状:RECTANGULAR封装形式:IN-LINE
并行/串行:SERIAL峰值回流温度(摄氏度):260
认证状态:Not Qualified座面最大高度:5.334 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:MATTE TIN端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:7.62 mm
Base Number Matches:1

AT17LV512A-10PL 数据手册

 浏览型号AT17LV512A-10PL的Datasheet PDF文件第2页浏览型号AT17LV512A-10PL的Datasheet PDF文件第3页浏览型号AT17LV512A-10PL的Datasheet PDF文件第4页浏览型号AT17LV512A-10PL的Datasheet PDF文件第5页浏览型号AT17LV512A-10PL的Datasheet PDF文件第6页浏览型号AT17LV512A-10PL的Datasheet PDF文件第7页 
Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1- and  
2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for  
Altera® FLEX® and APEXFPGAs (Device Selection Guide Included)  
Available as a 3.3V ( 10%) and 5.0V ( 5% Commercial, 10% Industrial) Version  
In-System Programmable (ISP) via 2-wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX, APEX  
Devices, ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200, Spartan®, VirtexFPGAs,  
Motorola MPA1000 FPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Very Low-power CMOS EEPROM Process  
Programmable Reset Polarity  
Available 8-lead PDIP, 20-lead PLCC and 32-lead TQFP Packages (Pin Compatible  
Across Product Family)  
FPGA  
Configuration  
EEPROM  
Memory  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
AT17LV65A  
AT17LV128A  
AT17LV256A  
AT17LV512A  
AT17LV010A  
AT17LV002A  
– Endurance: 100,000 Write Cycles  
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for  
Commercial Parts (at 70°C)  
Green (Pb/Halide-free/RoHS Compliant) Package Options Available  
1. Description  
The AT17A series FPGA configuration EEPROMs (Configurators) provide an easy-to-  
use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17A series device is packaged in the 8-lead PDIP(1), 20-lead PLCC and 32-lead  
TQFP, see Table 1-1. The AT17A series configurator uses a simple serial-access pro-  
cedure to configure one or more FPGA devices. The user can select the polarity of the  
reset function by programming four EEPROM bytes.These devices also support a  
write-protection mechanism within its programming mode.  
3.3V and 5V  
System Support  
Note:  
1. The 8-lead LAP, PDIP and SOIC packages for the AT17LV65A/128A/256A do not  
have an A label. However, the 8-lead packages are pin compatible with the 8-lead  
package of Altera’s EEPROMs, refer to the AT17LV65/128/256/512/010/002/040  
datasheet available on the Atmel web site for more information.  
The AT17A series configurators can be programmed with industry-standard program-  
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
Table 1-1.  
AT17A Series Packages  
AT17LV65A/  
AT17LV128A/  
Package  
AT17LV256A  
AT17LV512A  
AT17LV010A  
AT17LV002A  
8-lead  
PDIP  
Yes  
Yes  
Yes  
Yes  
20-lead  
PLCC  
Yes  
Yes  
Yes  
Yes  
Yes  
32-lead  
TQFP  
2322G–CNFG–03/06  

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