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AT17LV65-10SJ PDF预览

AT17LV65-10SJ

更新时间: 2024-10-27 19:32:55
品牌 Logo 应用领域
爱特美尔 - ATMEL 时钟光电二极管内存集成电路
页数 文件大小 规格书
29页 414K
描述
Configuration Memory, 64KX1, Serial, CMOS, PDSO20, 0.300 INCH, PLASTIC, MS-013AC, SOIC-20

AT17LV65-10SJ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, PLASTIC, MS-013AC, SOIC-20
针数:20Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.83其他特性:IT CAN OPERATES ON 4.75-5.25 RANGE SUPPLY VOLTAGE ALSO
最大时钟频率 (fCLK):10 MHzJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.8 mm
内存密度:65536 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1湿度敏感等级:2
功能数量:1端子数量:20
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX1
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.5 mmBase Number Matches:1

AT17LV65-10SJ 数据手册

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Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,  
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration  
Programs for Field Programmable Gate Arrays (FPGAs)  
Supports both 3.3V and 5.0V Operating Voltage Applications  
In-System Programmable (ISP) via Two-Wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera® FLEX®, APEX™  
Devices, ORCA®, Xilinx® XC3000, XC4000, XC5200, Spartan®, VirtexFPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Very Low-power CMOS EEPROM Process  
FPGA  
Configuration  
EEPROM  
Memory  
Programmable Reset Polarity  
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC  
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and  
44-lead TQFP Packages  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
AT17LV65  
– Endurance: 100,000 Write Cycles  
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for  
Commercial Parts (at 70°C)  
AT17LV128  
AT17LV256  
AT17LV512  
AT17LV010  
AT17LV002  
AT17LV040  
Green (Pb/Halide-free/RoHS Compliant) Package Options Available  
1. Description  
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-  
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-  
lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1-1. The  
AT17LV series Configurators uses a simple serial-access procedure to configure one  
or more FPGA devices. The user can select the polarity of the reset function by pro-  
gramming four EEPROM bytes. These devices also support a write-protection  
mechanism within its programming mode.  
3.3V and 5V  
System Support  
The AT17LV series configurators can be programmed with industry-standard pro-  
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
2321H–CNFG–03/06  

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