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AT17LV65-10CL PDF预览

AT17LV65-10CL

更新时间: 2024-10-27 13:05:39
品牌 Logo 应用领域
爱特美尔 - ATMEL 存储可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
24页 218K
描述
Configuration Memory, 64KX1, Serial, CMOS, 6 X 6 MM, 1.04 MM HEIGHT, 1.27 MM PITCH, LAP-8

AT17LV65-10CL 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SON,
针数:8Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.51
风险等级:5.83Is Samacsys:N
其他特性:IT CAN OPERATES ON 4.75-5.25 RANGE SUPPLY VOLTAGE ALSO最大时钟频率 (fCLK):10 MHz
JESD-30 代码:S-XDSO-N8长度:5.99 mm
内存密度:65536 bit内存集成电路类型:CONFIGURATION MEMORY
内存宽度:1功能数量:1
端子数量:8字数:65536 words
字数代码:64000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:64KX1封装主体材料:UNSPECIFIED
封装代码:SON封装形状:SQUARE
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.14 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:COPPER NICKEL GOLD
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:5.99 mmBase Number Matches:1

AT17LV65-10CL 数据手册

 浏览型号AT17LV65-10CL的Datasheet PDF文件第2页浏览型号AT17LV65-10CL的Datasheet PDF文件第3页浏览型号AT17LV65-10CL的Datasheet PDF文件第4页浏览型号AT17LV65-10CL的Datasheet PDF文件第5页浏览型号AT17LV65-10CL的Datasheet PDF文件第6页浏览型号AT17LV65-10CL的Datasheet PDF文件第7页 
Features  
EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,  
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration  
Programs for Field Programmable Gate Arrays (FPGAs)  
Supports both 3.3V and 5.0V Operating Voltage Applications  
In-System Programmable (ISP) via Two-Wire Bus  
Simple Interface to SRAM FPGAs  
Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™  
Devices, Lucent ORCA®, Xilinx XC3000, XC4000, XC5200, Spartan®, Virtex® FPGAs  
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays  
Very Low-power CMOS EEPROM Process  
FPGA  
Programmable Reset Polarity  
Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC  
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and  
44-lead TQFP Packages  
Emulation of Atmel’s AT24CXXX Serial EEPROMs  
Low-power Standby Mode  
High-reliability  
Configuration  
EEPROM  
Memory  
– Endurance: 100,000 Write Cycles  
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for  
Commercial Parts (at 70°C)  
AT17LV65  
Description  
AT17LV128  
AT17LV256  
AT17LV512  
AT17LV010  
AT17LV002  
AT17LV040  
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-  
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The  
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-  
lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The  
AT17LV series Configurators uses a simple serial-access procedure to configure one  
or more FPGA devices. The user can select the polarity of the reset function by pro-  
gramming four EEPROM bytes. These devices also support a write-protection  
mechanism within its programming mode.  
The AT17LV series configurators can be programmed with industry-standard program-  
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.  
Table 1. AT17LV Series Packages  
3.3V and 5V  
System Support  
AT17LV65/  
AT17LV128/  
AT17LV256  
AT17LV512/  
AT17LV010  
Package  
AT17LV002  
AT17LV040  
(3)  
8-lead LAP  
Yes  
Yes  
Yes  
Yes  
Yes(2)  
Yes  
Yes  
Yes  
8-lead PDIP  
8-lead SOIC  
20-lead PLCC  
20-lead SOIC  
44-lead PLCC  
44-lead TQFP  
(1)  
(1)  
(3)  
Use 8-lead LAP  
Use 8-lead LAP  
Yes  
Yes(2)  
Yes  
Yes(2)  
Yes  
Yes  
Yes  
Yes  
Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-  
lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-  
ble to use an 8-lead LAP package instead.  
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the  
AT17LV512/010/002 devices.  
Rev. 2321E–CNFG–06/03  
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.  

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