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AS8SLC512K32Q1-15L/IT PDF预览

AS8SLC512K32Q1-15L/IT

更新时间: 2024-02-28 07:42:27
品牌 Logo 应用领域
AUSTIN 存储静态存储器
页数 文件大小 规格书
12页 232K
描述
512K x 32 SRAM SRAM Memory Array MCM

AS8SLC512K32Q1-15L/IT 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:QFP
包装说明:QFP, QFP68,.99SQ,50针数:68
Reach Compliance Code:compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.09
最长访问时间:15 nsI/O 类型:COMMON
JESD-30 代码:S-CQFP-G68JESD-609代码:e0
长度:22.352 mm内存密度:16777216 bit
内存集成电路类型:SRAM MODULE内存宽度:32
功能数量:1端子数量:68
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:512KX32
输出特性:3-STATE封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QFP封装等效代码:QFP68,.99SQ,50
封装形状:SQUARE封装形式:FLATPACK
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:4.9784 mm最大待机电流:0.036 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.2 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:GULL WING端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:22.352 mmBase Number Matches:1

AS8SLC512K32Q1-15L/IT 数据手册

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SRAM  
AS8SLC512K32  
Austin Semiconductor, Inc.  
LOW POWER CHARACTERISTICS (L Version Only)  
DESCRIPTION  
CONDITIONS  
SYMBOL  
MIN  
MAX  
UNITS  
NOTES  
VCC for Retention Data  
VDR  
2
V
All Inputs @ Vcc + 0.2V  
or Vss + 0.2V,  
V
CC = 2V  
CC = 3V  
ICCDR  
ICCDR  
24  
32  
mA  
mA  
Data Retention Current  
V
CS\ = Vcc + 0.2V  
Chip Deselect to Data  
Retention Time  
0
ns  
4
t
CDR  
Operation Recovery Time  
20  
ms  
4, 11  
t
R
LOW VCC DATA RETENTION WAVEFORM  
DATA RETENTION MODE  
VCC  
4.5V  
4.5V  
VDR > 2V  
tCDR  
tR  
VDR  
CS\ 1-4  
NOTES  
1. All voltages referenced to VSS (GND).  
2. Worst case address switching.  
7. At any given temperature and voltage condition,  
tHZCS, is less than tLZCS, and tHZWE is less than tLZWE  
.
3. ICC is dependent on output loading and cycle rates.  
8. WE\ is HIGH for READ cycle.  
9. Device is continuously selected. Chip selects and  
output enable are held in their active state.  
10. Address valid prior to or coincident with latest  
occurring chip enable.  
11. tRC= READ cycle time.  
12. Chip enable (CS\) and write enable (WE\) can initiate  
and terminate a WRITE cycle.  
1
HZ.  
unloaded, and f=  
t
RC(MIN)  
The specified value applies with the outputs  
4. This parameter guaranteed but not tested.  
5. Test conditions as specified with output loading as  
shown in Fig. 1 & 2 unless otherwise noted.  
6. tHZCS, tHZOE and tHZWE are specified with CL= 5pF as in  
Fig. 2. Transition is measured +/- 200 mV typical from  
steady state voltage, allowing for actual tester RC time  
constant.  
13. ICC is for full 32 bit mode.  
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.  
AS8SLC512K32  
Rev. 2.5 5/09  
5

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