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AS7C513B-20TI PDF预览

AS7C513B-20TI

更新时间: 2024-02-19 13:56:39
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 215K
描述
5V 32K x 16 CMOS SRAM

AS7C513B-20TI 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:unknown
ECCN代码:3A991.B.2.BHTS代码:8542.32.00.41
风险等级:5.8Is Samacsys:N
最长访问时间:20 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G44JESD-609代码:e0
长度:18.415 mm内存密度:524288 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:32768 words字数代码:32000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:32KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):240
电源:5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.01 A
最小待机电流:4.5 V子类别:SRAMs
最大压摆率:0.08 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:10.16 mmBase Number Matches:1

AS7C513B-20TI 数据手册

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AS7C513B  
®
Write waveform 2 (CE controlled)11  
tWC  
Address  
tAH  
& tWR  
tAS  
tCW  
CE  
tAW  
tBW  
LB, UB  
WE  
tWP  
tDH  
tDW  
Data valid  
Data IN  
tWZ  
Data undefined  
tOW  
tCLZ  
Data OUT  
High-Z  
High-Z  
AC test conditions  
- Output load: see Figure B.  
Thevenin equivalent:  
- Input pulse level: GND to 3.5V. See Figure A.  
- Input rise and fall times: 2 ns. See Figure A.  
- Input and output timing reference levels: 1.5V.  
168Ω  
Dout  
+1.728V  
+5.0V  
480Ω  
Dout  
255Ω  
+3.5V  
C13  
90%  
10%  
90%  
10%  
2 ns  
Figure A: Input pulse  
GND  
GND  
Figure B: 5.0V Output load  
Notes  
1
2
3
4
5
6
7
8
9
During VCC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.  
This parameter is sampled, but not 100% tested.  
For test conditions, see AC Test Conditions, Figures A and B.  
These parameters are specified with CL = 5pF, as in Figure B. Transition is measured ±500mV from steady-state voltage.  
This parameter is guaranteed, but not 100% tested.  
WE is High for read cycle.  
CE and OE are Low for read cycle.  
Address valid prior to or coincident with CE transition Low.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 Not applicable.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 Not applicable.  
13 C=30pF, except on High Z and Low Z parameters, where C=5pF.  
3/26/04, v.1.3  
Alliance Semiconductor  
P. 6 of 9  

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