Datasheet > 存储 > SRAM> AS7C34096A-20JI

AS7C34096A-20JI

更新时间： 2024-09-16 22:56:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	158K
描述
3.3V 512K x 8 CMOS SRAM

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中文翻译

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数据手册

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AS7C34096A-20JI 数据手册

August 2004

AS7C34096A

3.3V 512K × 8 CMOS SRAM

• Equal access and cycle times

Features

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil 36-pin SOJ

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

OE inputs

• Pin compatible to AS7C34096

• Industrial and commercial temperature

• Organization: 524,288 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 4/5/6/7 ns output enable access time

• Low power consumption: ACTIVE

- 650 mW / max @ 10 ns

Pin arrangements

36-pin SOJ (400 mil)

• Low power consumption: STANDBY

- 28.8 mW / max CMOS

A18

A17

A16

A15

Logic block diagram

I/O1

I/O2

V_CC

I/O8

I/O7

GND

V_CC

I/O6

I/O5

A14

A13

A12

A11

A10

GND

I/O3

I/O4

V_CC

GND

Input buffer

I/O1

I/O8

524,288 × 8

Array

(4,194,304)

44-pin TSOP 2

A18

A17

A16

A15

Column decoder

Control

Circuit

I/O1

I/O2

V_CC

I/O8

I/O7

GND

V_CC

GND

I/O3

I/O4

I/O6

I/O5

A14

A13

A12

A11

A10

Selection guide

–10

–12

–15

–20

Unit

Maximum address access time

Maximum outputenable access time

Industrial

180

170

160

150

140

130

110

100

Maximum operating current

Commercial

Maximum CMOS standby current

8/17/04, v. 2.1

Alliance Semiconductor

P. 1 of 9

12 3 4 5 6 7...9

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