AS7C4098
AS7C34098
November 2001
®
5V/3.3V 256K × 16 CMOS SRAM
Features
• AS7C4098 (5V version)
• Low power consumption: STANDBY
• AS7C34098 (3.3V version)
• Industrial and commercial temperature
• Organization: 262,144 words × 16 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4098)/max @ 12 ns
- 468 mW (AS7C34098)/max @ 12 ns
- 110 mW (AS7C4098)/max CMOS
- 72 mW (AS7C34098)/max CMOS
• Individual byte read/write controls
• Easy memory expansion with CE, OE inputs
• TTL- and CMOS-compatible, three-state I/O
• 44-pin JEDEC standard packages
- 400-mil SOJ
- TSOP 2
- 48-ball FBGA 7 x 11 mm
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Logic block diagram
Pin arrangement
48-CSP Ball-Grid-Array Package
A0
44-pin SOJ (400 mil),
TSOP 2
V
A1
A2
CC
1
2
3
4
5
6
1024 × 256 × 16
Array
GND
A3
A
B
LB
OE
A0 A1
A3 A4
A2
CS
NC
A4
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
A17
A6
2
A16
(4,194,304)
A2
3
A15
A7
I/O9 UB
I/O1
A3
4
OE
A8
A4
5
UB
A12
A13
C I/O10 I/O11 A5 A6 I/O2 I/O3
CE
6
LB
I/O16
I/O15
I/O14
I/O13
GND
VCC
I/O1
I/O2
I/O3
I/O4
VCC
7
D
E
VSS I/O12 A17 A7 I/O4 VCC
VCC I/O13 NC A16 I/O5 VSS
8
I/O1–I/O8
I/O
buffer
Control circuit
9
I/O9–I/O16
10
11
12
13
14
15
GND
I/O5
I/O6
I/O7
Column decoder
WE
F I/O15 I/O14 A14 A15 I/O6 I/O7
G I/O16 NC A12 A13 WE I/O8
I/O12
I/O11
I/O10
I/O8
WE
A5
16
17
18
19
20
21
22
29
28
27
26
I/O9
NC
H
NC
A8
A9 A10 A11
NC
UB
OE
LB
A14
A13
A12
A11
A10
A6
A7
25
24
23
A8
A9
CE
Selection guide
–10
10
5
–12
12
–15
–20
20
Unit
ns
Maximum address access time
15
7
Maximum output enable access time
6
9
ns
AS7C4098
AS7C34098
AS7C4098
AS7C34098
–
250
130
20
220
110
20
180
100
20
mA
mA
mA
mA
Maximum operating current
160
–
Maximum CMOS standby current
20
20
20
20
11/28/01; v.1.6
Alliance Semiconductor
P. 1 of 11
Copyright © Alliance Semiconductor. All rights reserved.