August 2004
AS7C34096A
®
3.3V 512K × 8 CMOS SRAM
• Equal access and cycle times
Features
• Easy memory expansion with CE
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
,
OE inputs
• Pin compatible to AS7C34096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 4/5/6/7 ns output enable access time
• Low power consumption: ACTIVE
- 650 mW / max @ 10 ns
Pin arrangements
36-pin SOJ (400 mil)
• Low power consumption: STANDBY
- 28.8 mW / max CMOS
A0
A1
A2
A3
A4
CE
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
A18
A17
A16
A15
OE
3
4
5
Logic block diagram
6
I/O1
I/O2
VCC
7
I/O8
I/O7
GND
VCC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
8
9
GND
I/O3
I/O4
WE
A5
10
11
12
13
14
15
16
17
18
VCC
GND
Input buffer
A6
A7
A8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A9
I/O1
I/O8
524,288 × 8
Array
(4,194,304)
44-pin TSOP 2
NC
NC
NC
NC
A18
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
A0
A1
A2
A3
A4
CE
2
3
4
A17
A16
A15
OE
5
6
7
Column decoder
WE
OE
CE
Control
Circuit
8
I/O1
I/O2
VCC
I/O8
I/O7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
VCC
GND
I/O3
I/O4
WE
A5
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A6
A7
A8
A9
NC
NC
NC
NC
Selection guide
–10
10
4
–12
12
5
–15
15
6
–20
20
7
Unit
ns
Maximum address access time
Maximum outputenable access time
ns
Industrial
180
170
8
160
150
8
140
130
8
110
100
8
mA
mA
mA
Maximum operating current
Commercial
Maximum CMOS standby current
8/17/04, v. 2.1
Alliance Semiconductor
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