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AS7C3364NTD32B-200TQC PDF预览

AS7C3364NTD32B-200TQC

更新时间: 2024-11-18 20:13:19
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
19页 437K
描述
ZBT SRAM, 64KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C3364NTD32B-200TQC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.53
最长访问时间:3 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:2097152 bit
内存集成电路类型:ZBT SRAM内存宽度:32
功能数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:64KX32
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

AS7C3364NTD32B-200TQC 数据手册

 浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第2页浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第3页浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第4页浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第5页浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第6页浏览型号AS7C3364NTD32B-200TQC的Datasheet PDF文件第7页 
April 2005  
AS7C3364NTD32B  
AS7C3364NTD36B  
®
3.3V 64K×32/36 Pipelined SRAM with NTDTM  
Features  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Organization: 65,536 words × 32 or 36 bits  
• NTDarchitecture for efficient bus operation  
• Fast clock speeds to 200 MHz  
• Fast clock to data access: 3.0/3.5/4.0 ns  
• Fast OE access time: 3.0/3.5/4.0 ns  
• Fully synchronous operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Byte write enables  
• Interleaved or linear burst modes  
• Snooze mode for reduced power standby  
Logic block diagram  
16  
16  
Q
DAddress  
register  
Burst logic  
A[15:0]  
16  
16  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
16  
addr. registers  
CLK  
R/W  
BWa  
BWb  
BWc  
BWd  
Control  
logic  
CLK  
ADV / LD  
128K x 32/36  
SRAM  
Array  
LBO  
ZZ  
CLK  
32/36  
32/36  
Data  
DQ [a:d]  
Q
D
Input  
Register  
CLK  
32/36  
32/36  
32/36  
CLK  
CEN  
CLK  
Output  
Register  
OE  
32/36  
OE  
DQ [a:d]  
Selection Guide  
-200  
-166  
6
-133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
5
Maximum clock frequency  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
200  
3.0  
375  
135  
30  
166  
3.5  
350  
120  
30  
MHz  
ns  
325  
110  
30  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
4/28/05; v.1.3  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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