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AS7C3364NTF32B-80TQCN PDF预览

AS7C3364NTF32B-80TQCN

更新时间: 2024-02-23 09:16:13
品牌 Logo 应用领域
ALSC 内存集成电路静态存储器
页数 文件大小 规格书
19页 418K
描述
3.3V 64K x 32/36 Flowthrough Synchronous SRAM with NTD

AS7C3364NTF32B-80TQCN 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFP包装说明:LQFP,
针数:100Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.53Is Samacsys:N
最长访问时间:8 ns其他特性:FLOW-THROUGH ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e3
长度:20 mm内存密度:2097152 bit
内存集成电路类型:ZBT SRAM内存宽度:32
功能数量:1端子数量:100
字数:65536 words字数代码:64000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:64KX32
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):250
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:14 mm
Base Number Matches:1

AS7C3364NTF32B-80TQCN 数据手册

 浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第2页浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第3页浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第4页浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第5页浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第6页浏览型号AS7C3364NTF32B-80TQCN的Datasheet PDF文件第7页 
April 2005  
AS7C3364NTF32B  
AS7C3364NTF36B  
®
3.3V 64K × 32/36 Flowthrough Synchronous SRAM with NTDTM  
Features  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Self-timed write cycles  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Organization: 65,536 words × 32 or 36 bits  
• NTD architecture for efficient bus operation  
DDQ  
• Fast clock to data access: 7.5/8.0/10.0 ns  
• Fast OE access time: 3.5/4.0 ns  
• Fully synchronous operation  
• Flow-through mode  
• Asynchronous output enable control  
• Available in 100-pin TQFP package  
• Byte write enables  
• Clock enable for operation hold  
Logic block diagram  
16  
16  
A[15:0]  
Q
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
CLK  
16  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
BWc  
BWd  
ADV / LD  
LBO  
64K x 32/36  
SRAM  
ZZ  
CLK  
Array  
32/36  
32/36  
DQ[a,b,c,d]  
Data  
Input  
Register  
D
Q
32/36  
32/36  
CLK  
32/36  
CLK  
CEN  
Output  
Buffer  
OE  
32/36  
OE  
DQ[a,b,c,d]  
Selection guide  
-75  
-80  
10  
-10  
12  
Units  
ns  
Minimum cycle time  
8.5  
7.5  
260  
110  
30  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
8.0  
230  
100  
30  
10  
ns  
200  
90  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
30  
4/28/05, v 1.0  
Alliance Semiconductor  
P. 1 of 19  
Copyright © Alliance Semiconductor. All rights reserved.  

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