Datasheet > 暂无类别数据> AS7C33512PFD32A-166TQC

AS7C33512PFD32A-166TQC

更新时间： 2024-01-02 08:49:46

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

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技术参数
数据手册

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AS7C33512PFD32A-166TQC 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	LQFP,	针数：	100
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.66
最长访问时间：	3.4 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PQFP-G100	JESD-609代码：	e3
长度：	20 mm	内存密度：	16777216 bit
内存集成电路类型：	STANDARD SRAM	内存宽度：	32
功能数量：	1	端子数量：	100
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX32
封装主体材料：	PLASTIC/EPOXY	封装代码：	LQFP
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	245
认证状态：	Not Qualified	座面最大高度：	1.6 mm
最大供电电压 (Vsup)：	3.465 V	最小供电电压 (Vsup)：	3.135 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
Base Number Matches：	1

AS7C33512PFD32A-166TQC 数据手册

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AS7C33512PFD32A

AS7C33512PFD36A

Functional description

The AS7C33512PFD32A/36A is a high-performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) device

organized as 524,288 words x 32/36. It incorporates a two-stage register-register pipeline for highest frequency on any given technology.

Fast cycle times of 6/7.5 ns with clock access times (t_CD) of 3.4/3.8 ns enable 166, and 133 MHz bus frequencies. Three chip enable (CE)

inputs permit easy memory expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor

address strobe (ADSP). The burst advance pin (ADV) allows subsequent internally generated burst addresses.

Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register

when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data

accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out registers and driven

on the output pins on the next positive edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted, but is sampled on all

subsequent clock edges. Address is incremented internally for the next access of the burst when ADV is sampled low and both address

strobes are high. Burst mode is selectable with the LBO input. With LBO unconnected or driven high, burst operations use an interleaved

count sequence. With LBO driven low, the device uses a linear count sequence.

Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all 32/

36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting BWE

and the appropriate individual byte BWn signals.

BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when

BWn is sampled lOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented

internally to the next burst address if BWn and ADV are sampled low. This device operates in double-cycle deselect feature during read

cycles.

Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are

as follows:

• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.

• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).

• Master chip enable CE0 blocks ADSP, but not ADSC.

The AS7C33512PFD32A/36A family operates from a core 3.3V power supply. I/Os use a separate power supply that can operate at 2.5V or

3.3V. These devices are available in a 100-pin TQFP package.

TQFP capacitance

Parameter

Input capacitance

I/O capacitance

Symbol

Test conditions

V_IN= 0V

Min

Max

Unit

C_IN

C_I/O

V_OUT= 0V

* Guaranteed not tested

TQFP thermal resistance

Description

Conditions

Symbol

θ_JA

Typical

Units

°C/W

1–layer

4–layer

Thermal resistance

(junction to ambient)¹

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51

θ_JA

Thermal resistance

(junction to top of case)¹

θ_JC

°C/W

1 This parameter is sampled

2/10/05, v 1.3

Alliance Semiconductor

4 of 19

1 2 345 6 7...19

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与AS7C33512PFD32A-166TQC相关器件

型号	品牌	描述	获取价格	数据表
AS7C33512PFD32A-166TQCN	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFD32A-166TQI	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFD32A-166TQIN	ALSC	3.3V 512K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33512PFD32A-200BC	ALSC	Standard SRAM, 512KX32, 3ns, CMOS, PBGA119, BGA-119	获取价格
AS7C33512PFD32A-200BI	ALSC	Standard SRAM, 512KX32, 3ns, CMOS, PBGA119, BGA-119	获取价格
AS7C33512PFD32A-200TQC	ALSC	Standard SRAM, 512KX32, 3ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100	获取价格

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