Datasheet > 存储 > SRAM> AS7C33512PFD36A-133TQCN

AS7C33512PFD36A-133TQCN

更新时间： 2024-01-22 16:59:44

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	542K
描述
3.3V 512K x 32/36 pipelined burst synchronous SRAM

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AS7C33512PFD36A-133TQCN 数据手册

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February 2005

AS7C33512PFD32A

AS7C33512PFD36A

3.3V 512K × 32/36 pipelined burst synchronous SRAM

Features

• Organization: 524,288 words × 32 or 36 bits

• Fast clock speeds to 166 MHz

• Fast clock to data access: 3.4/3.8 ns

• Fast OE access time: 3.4/3.8 ns

• Fully synchronous register-to-register operation

• Double-cycle deselect

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 3.3V core power supply

• 2.5V or 3.3V I/O operation with separate V

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

DDQ

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

CLR

512K × 32/36

Memory

array

CLK

A[18:0]

Address

36/32

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

BW_a

CLK

CE0

CE1

Output

registers

CLK

CE2

Input

registers

CLK

Enable

CLK

Enable

delay

CLK

Power

down

36/32

DQ[a:d]

Selection guide

-166

-133

7.5

133

3.8

275

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

166

3.4

300

MHz

Maximum CMOS standby current (DC)

2/10/05, v 1.3

Alliance Semiconductor

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