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AS7C33512PFD18A2-150BC PDF预览

AS7C33512PFD18A2-150BC

更新时间: 2024-11-25 03:45:11
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
14页 370K
描述
Standard SRAM, 512KX18, 4.3ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

AS7C33512PFD18A2-150BC 数据手册

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April 2002  
Preliminary  
AS7C33512PFD16A  
AS7C33512PFD18A  
®
3.3V 512K × 16/18 pipeline burst synchronous SRAM  
Features  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 119-pin BGA package  
• Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/O operation with separate V  
• Organization: 524,288 words × 16 or 18 bits  
• Fast clock speeds to 166 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.5/3.8/4.0/5.0 ns  
• Fast OE access time: 3.5/3.8/4.0/5.0 ns  
• Fully synchronous register-to-register operation  
• Single register “Flow-through” option  
• Dual-cycle deselect  
DDQ  
• 30 mW typical standby power in power down mode  
1
• NTD™ pipeline architecture available  
- Single-cycle deselect also available (AS7C33512PFS16A/  
AS7C33512PFS18A)  
(AS7C33512NTD16A/AS7C33512NTD18A)  
• Available in both 2 chip enable and 3 chip enable  
- 2 CE part number is AS7C33512PFD16A or AS7C33512PFD18A2  
• Pentium® compatible architecture and timing  
*
®
1. Pentium is a registered trademark of Intel Corporation. NTD™ is a  
trademark of Alliance Semiconductor Corporation. All trademarks men-  
tioned in this document are the property of their respective owners.  
1
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
CLR  
Burst logic  
19 17  
512K × 16/18  
Memory  
ADSC  
ADSP  
19  
19  
AddressQ  
D
array  
A[18:0]  
CS  
register  
CLK  
16/18  
16/18  
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
BWE  
BW  
CLK  
D
Q
DQa  
2
Byte Write  
a
registers  
CLK  
CE0  
CE1  
CE2  
OE  
D
Enable Q  
register  
Input  
registers  
Output  
registers  
CE  
CLK  
CLK  
CLK  
D
Enable Q  
delay  
register  
Power  
down  
ZZ  
CLK  
OE  
16/18  
DQ[a,b]  
FT  
Selection guide  
–166  
–150  
–133  
–100  
10  
Units  
ns  
Minimum cycle time  
6
6.6  
150  
3.8  
450  
110  
30  
7.5  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
166.7  
3.5  
133.3  
4
100  
5
MHz  
ns  
475  
130  
30  
425  
100  
30  
325  
90  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
30  
4/15/02; 4 v.1.5  
Alliance Semiconductor  
1 of 14  
Copyright © Alliance Semiconductor. All rights reserved.  

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