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AS7C33256PFD36A-150BI PDF预览

AS7C33256PFD36A-150BI

更新时间: 2024-10-29 03:26:35
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
14页 584K
描述
Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119

AS7C33256PFD36A-150BI 数据手册

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AS7C33256PFD32A  
AS7C33256PFD36A  
®
Signal descriptions  
Signal  
I/O Properties Description  
CLK  
I
I
CLOCK  
SYNC  
SYNC  
Clock. All inputs except OE, FT, ZZ, LBO are synchronous to this clock.  
Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.  
Data. Driven as output when the chip is enabled and OE is active.  
A0–A17  
DQ[a,b,c,d] I/O  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is  
inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more information.  
CE0  
I
I
I
SYNC  
SYNC  
SYNC  
Synchronous chip enables. Active HIGH and active Low, respectively. Sampled on clock  
edges when ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
Address strobe processor. Asserted LOW to load a new bus address or to enter standby  
mode.  
ADSC  
ADV  
I
I
SYNC  
SYNC  
Address strobe controller. Asserted LOW to load a new address or to enter standby mode.  
Advance. Asserted LOW to continue burst read/write.  
Global write enable. Asserted LOW to write all 32/36 bits. When High, BWE and BW[a:d]  
control write enable.  
GWE  
BWE  
I
I
SYNC  
SYNC  
Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d] inputs.  
Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =  
Low. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a write  
cycle. If all BW[a:d] are inactive the cycle is a read cycle.  
BW[a,b,c,d]  
I
SYNC  
Asynchronous output enable. I/O pins are driven when OE is active and the chip is in read  
mode.  
OE  
I
I
ASYNC  
STATIC  
Count mode. When driven High, count sequence follows Intel XOR convention. When  
driven Low, count sequence follows linear convention. This signal is internally pulled High.  
LBO  
Flow-through mode.When low, enables single register flow-through mode. Connect to  
FT  
ZZ  
I
I
STATIC  
ASYNC  
VDD if unused or for pipelined operation.  
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
Absolute maximum ratings  
Parameter  
Symbol  
VDD, VDDQ  
VIN  
Min  
–0.5  
–0.5  
–0.5  
Max  
+4.6  
Unit  
V
Power supply voltage relative to GND  
Input voltage relative to GND (input pins)  
Input voltage relative to GND (I/O pins)  
Power dissipation  
VDD + 0.5  
VDDQ + 0.5  
1.8  
V
VIN  
V
PD  
W
mA  
oC  
oC  
DC output current  
IOUT  
50  
Storage temperature (plastic)  
Temperature under bias  
Tstg  
–65  
–65  
+150  
Tbias  
+135  
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of  
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum  
rating conditions may affect reliability.  
4/15/02; v.1.8  
Alliance Semiconductor  
P. 5 of 14  

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