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AS7C33256PFD36A-133TQI PDF预览

AS7C33256PFD36A-133TQI

更新时间： 2024-02-29 23:17:03
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美国芯成 - ISSI 静态存储器内存集成电路
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20页 527K
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AS7C33256PFD36A-133TQI 数据手册

 浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第4页浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第5页浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第6页浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第8页浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第9页浏览型号AS7C33256PFD36A-133TQI的Datasheet PDF文件第10页 
AS7C33256PFD32A  
AS7C33256PFD36A  
®
[4]  
Synchronous truth table  
[2]  
CE01  
H
L
CE1  
X
L
CE2  
X
X
X
H
H
L
ADSP ADSC ADV WRITE  
OE  
X
X
X
X
X
L
Address accessed  
NA  
CLK  
Operation  
Deselect  
DQ  
Hi−Z  
Hi−Z  
Hi−Z  
Hi−Z  
Hi−Z  
Q
X
L
L
X
L
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
L
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
L to H  
NA  
Deselect  
L
L
H
L
NA  
Deselect  
L
X
X
H
H
H
H
X
X
X
X
X
X
X
X
H
X
X
X
X
X
L
NA  
Deselect  
L
H
L
NA  
Deselect  
L
X
X
L
External  
External  
External  
External  
Next  
Begin read  
L
L
L
H
L
Begin read  
Hi−Z  
Q
L
L
H
H
H
H
H
H
X
X
X
X
H
H
X
H
X
Begin read  
L
L
L
H
L
Begin read  
Hi−Z  
Q
X
X
X
X
H
H
H
H
L
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
H
H
L
Continue read  
Continue read  
Suspend read  
Suspend read  
Continue read  
Continue read  
Suspend read  
Suspend read  
Begin write  
Continue write  
Continue write  
Suspend write  
Suspend write  
L
H
L
Next  
Hi−Z  
Q
H
H
L
Current  
Current  
Next  
H
L
Hi−Z  
Q
L
H
L
Next  
Hi−Z  
Q
H
H
X
L
Current  
Current  
External  
Next  
H
X
X
X
X
X
Hi−Z  
3
D
X
H
X
H
X
X
X
X
H
H
H
H
L
D
D
D
D
L
L
Next  
H
H
L
Current  
Current  
L
1 X = don’t care, L = low, H = high  
2 For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW or GWE is LOW. WRITE = HIGH for all  
BWx, BWE, GWE HIGH. See "Write enable truth table (per byte)," on page 6 for more information.  
3 For write operation following a READ, OE must be high before the input data set up time and held high throughout the input hold time  
4 ZZ pin is always Low.  
12/1/04, v.1.2  
Alliance Semiconductor  
P. 7 of 20  
1...45678910...20

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与AS7C33256PFD36A-133TQI相关器件

型号 品牌 获取价格 描述 数据表
AS7C33256PFD36A-133TQIN ALSC

获取价格

 		3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFD36A-133TQIN ISSI

获取价格

 		Standard SRAM, 256KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100
AS7C33256PFD36A-150BC ALSC

获取价格

 		Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119
AS7C33256PFD36A-150BI ALSC

获取价格

 		Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119
AS7C33256PFD36A-166BC ALSC

获取价格

 		Standard SRAM, 256KX36, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119
AS7C33256PFD36A-166BI ALSC

获取价格

 		Standard SRAM, 256KX36, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119
AS7C33256PFD36A-166TQC ALSC

获取价格

 		3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFD36A-166TQC ISSI

获取价格

 		Standard SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C33256PFD36A-166TQCN ALSC

获取价格

 		3.3V 256K x 32/36 pipelined burst synchronous SRAM
AS7C33256PFD36A-166TQCN ISSI

获取价格

 		Standard SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

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