Datasheet > AS7C33256PFD36A-133TQI

AS7C33256PFD36A-133TQI

更新时间： 2024-01-10 12:48:51

品牌	Logo	应用领域
美国芯成 - ISSI		静态存储器内存集成电路
页数	文件大小	规格书
20页	527K
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AS7C33256PFD32A

AS7C33256PFD36A

Signal descriptions

Signal

I/O Properties Description

CLK

CLOCK

SYNC

Clock. All inputs except OE, ZZ, LBO are synchronous to this clock.

Address. Sampled when all chip enables are active and ADSC or ADSP are asserted.

Data. Driven as output when the chip is enabled and OE is active.

A, A0, A1

DQ[a,b,c,d] I/O

Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0

is inactive, ADSP is blocked. Refer to the Synchronous Truth Table for more

information.

CE0

SYNC

Synchronous chip enables. Active HIGH and active LOW, respectively. Sampled on

clock edges when ADSC is active or when CE0 and ADSP are active.

CE1, CE2

ADSP

SYNC

Address strobe processor. Asserted LOW to load a new bus address or to enter standby

mode.

Address strobe controller. Asserted LOW to load a new address or to enter standby

mode.

ADSC

ADV

GWE

SYNC

Advance. Asserted LOW to continue burst read/write.

Global write enable. Asserted LOW to write all 32/36 bits. When HIGH, BWE and

BW[a:d] control write enable.

Byte write enable. Asserted LOW with GWE = HIGH to enable effect of BW[a:d]

inputs.

BWE

SYNC

Write enables. Used to control write of individual bytes when GWE = HIGH and BWE =

LOW. If any of BW[a:d] is active with GWE = HIGH and BWE = LOW the cycle is a

write cycle. If all BW[a:d] are inactive the cycle is a read cycle.

BW[a,b,c,d] I

Asynchronous output enable. I/O pins are driven when OE is active and the chip is in

read mode.

ASYNC

STATIC

Selects Burst mode. When tied to V or left floating, device follows Interleaved Burst

LBO

order. When driven Low, device follows linear Burst order. This signal is internally

pulled High.

ASYNC

Snooze. Places device in LOW power mode; data is retained. Connect to GND if unused.

No connect

Snooze Mode

SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to I_SB2. The duration of

SNOOZE MODE is dictated by the length of time the ZZ is in a High state.

The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.

When the ZZ pin becomes a logic High, I_SB2is guaranteed after the time t_ZZIis met. After entering SNOOZE MODE, all inputs except ZZ

is disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.

Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting

SNOOZE MODE during t_PUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE

MODE.

12/1/04, v.1.2

Alliance Semiconductor

P. 5 of 20

1 2 3 456 7 8...20

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与AS7C33256PFD36A-133TQI相关器件

型号	品牌	描述	获取价格	数据表
AS7C33256PFD36A-133TQIN	ALSC	3.3V 256K x 32/36 pipelined burst synchronous SRAM	获取价格
AS7C33256PFD36A-133TQIN	ISSI	Standard SRAM, 256KX36, 4ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100	获取价格
AS7C33256PFD36A-150BC	ALSC	Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFD36A-150BI	ALSC	Standard SRAM, 256KX36, 10ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFD36A-166BC	ALSC	Standard SRAM, 256KX36, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格
AS7C33256PFD36A-166BI	ALSC	Standard SRAM, 256KX36, 9ns, CMOS, PBGA119, 14 X 20 MM, BGA-119	获取价格

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