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AS7C33128PFS16B-133TQI PDF预览

AS7C33128PFS16B-133TQI

更新时间: 2024-11-18 20:37:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
14页 444K
描述
Standard SRAM, 128KX16, 10ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C33128PFS16B-133TQI 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.67
最长访问时间:10 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:R-PQFP-G100JESD-609代码:e0
长度:20 mm内存密度:2097152 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:100
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
封装主体材料:PLASTIC/EPOXY封装代码:LQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

AS7C33128PFS16B-133TQI 数据手册

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AS7C33128PFS16B  
AS7C33128PFS18B  
October 2003  
®
3.3V 128K × 16/18 pipeline burst synchronous SRAM  
Features  
Byte write enables  
Multiple chip enables for easy expansion  
3.3V core power supply  
2.5V or 3.3V I/O operation with separate V  
Organization: 131,072 words × 16 or 18 bits  
Fast clock speeds to 200 MHz in LVTTL/LVCMOS  
Fast clock to data access: 3.0/3.5/4.0 ns  
Fast OE access time: 3.0/3.5/4.0 ns  
Fully synchronous register-to-register operation  
Flow-through” or “Pipeline” mode  
Single-cycle deselect  
DDQ  
30 mW typical standby power in power down mode  
NTD™1 pipeline architecture available  
(AS7C33128NTD16B/AS7C33128NTD18B)  
Dual-cycle deselect also available (AS7C33128PFD16B/  
AS7C33128PFD18B)  
Pentium® compatible architecture and timing  
Asynchronous output enable control  
Economical 100-pin TQFP package  
1. Pentium® is a registered trademark of Intel Corporation. NTD™ is a  
trademark of Alliance Semiconductor Corporation. All trademarks men-  
tioned in this document are the property of their respective owners.  
1
Pin arrangement  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
A
NC  
NC  
NC  
1
80  
79  
78  
77  
76  
75  
74  
73  
72  
71  
70  
69  
68  
67  
66  
65  
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
Burst logic  
128K × 16/18  
Memory  
array  
ADSC  
ADSP  
NC  
NC  
V
2
CLR  
3
V
4
DDQ  
SSQ  
NC  
DDQ  
17  
Q
D
A[16:0]  
V
V
5
SSQ  
NC  
Address  
6
17  
CS  
15  
17  
register  
DQpa/NC  
DQa  
DQa  
NC  
7
CLK  
DQb  
DQb  
8
9
V
DDQ  
V
10  
11  
SSQ  
SSQ  
16/18 16/18  
V
V
DDQ  
DQa  
DQa  
VSS  
NC  
DQb 12  
DQb 13  
FT 14  
GWE  
D
Q
BytDeQWb rite  
BW  
b
TQFP 14 × 20mm  
registers  
V
15  
NC 16  
17  
DD  
BWE  
BW  
CLK  
V
DD  
ZZ  
V
D
Q
SS  
BytDeQWa rite  
registers  
DQa  
DQa  
DQb 18  
DQb 19  
2
a
V
SSQ  
V
20  
21  
DDQ  
DDQ  
CLK  
V
V
SSQ  
CE0  
CE1  
CE2  
DQa  
DQa  
NC  
DQb 22  
DQb 23  
OE  
DEnable  
Q
Input  
Output  
registers  
register  
DQpb/NC  
24  
registers  
NC  
NC 25  
CE  
CLK  
CLK  
CLK  
V
DDQ  
V
26  
27  
SSQ  
SSQ  
V
V
DDQ  
DEnable  
Q
NC  
NC  
NC  
NC 28  
NC 29  
NC 30  
Power  
down  
delay  
ZZ  
register  
CLK  
OE  
16/18  
DQ [a,b]  
FT  
Note: pins 24, 74 are NC for ×16.  
Selection guide  
–200  
5
–166  
6
–133  
7.5  
133  
4
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
200  
3
166  
3.5  
350  
100  
30  
MHz  
ns  
400  
120  
30  
325  
90  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
30  
10/29/03; v.1.0  
Alliance Semiconductor  
P. 1 of 14  
Copyright © Alliance Semiconductor. All rights reserved.  

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