Datasheet > 存储 > SRAM> AS7C31024-15TJI

AS7C31024-15TJI

更新时间： 2024-09-18 22:22:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
9页	199K
描述
5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS7C31024-15TJI 数据手册

AS7C1024

AS7C31024

Data retention characteristics (over the operating range)

Parameter

Symbol

Test conditions

Device

Min

2.0

–

Max

–

Unit

_CCfor data retention

VDR

V_CC= 2.0V

AS7C1024

Data retention current

ICCDR

CE1 ≥ V_CC–0.2V or

CE2 ≤ 0.2V

AS7C31024

–

Chip deselect to data retention time

Operation recovery time

tCDR

–

V ≥ V_CC–0.2V or

V ≤ 0.2V

t_RC

–

Input leakage current

| ILI |

µA

Data retention waveform

Data retention mode

≥

2.0V

CDR

CE1

AC test conditions

– 5V output load: see Figure B or Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

Thevenin equivalent:

168W

+1.728V (5V and 3.3V)

OUT

+5V

+3.3V

480W

320W

OUT

+3.0V

90%

10%

90%

10%

255W

C(14)

GND

255W

C(14)

GND

2 ns

Figure A: Input pulse

GND

Figure B: 5V Output load

Figure C: 3.3V Output load

Notes

During V power-up, a pull-up resistor to V on CE1 is required to meet I specification.

CC CC SB

This parameter is sampled and not 100% tested.

For test conditions, see AC Test Conditions, Figures A, B, and C.

and t are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.

CHZ

CLZ

This parameter is guaranteed, but not 100% tested.

WEis High for read cycle.

CE1 and OE are Low and CE2 is High for read cycle.

Address valid prior to or coincident with CE1 transition Low.

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 2V data retention applies to commercial temperature operating range only.

14 C=30pF, except all high Z and low Z parameters, C=5pF.

ALLIANCE SEMICONDUCTOR

11/ 29/ 00

1...3 4 567 8 9

中文翻译

下载PDF

与AS7C31024-15TJI相关器件

型号	品牌	获取价格	描述	数据表
AS7C31024-15TPC	ETC	获取价格	x8 SRAM
AS7C31024-20	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20HC	ALSC	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32
AS7C31024-20HI	ALSC	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32
AS7C31024-20JC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20JI	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20PC	ETC	获取价格	x8 SRAM
AS7C31024-20TC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20TI	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20TJC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)