Datasheet > 存储 > SRAM> AS7C31024-15JI

AS7C31024-15JI

更新时间： 2024-10-27 22:22:35

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器光电二极管
页数	文件大小	规格书
9页	199K
描述
5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

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AS7C31024-15JI 数据手册

AS7C1024

AS7C31024

Functional description

The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices

organized as 131,072 words × 8 bits. It is designed for memory applications where fast data access, low power, and simple

interfacing are desired.

Equal address access and cycle times (t_AA, t_RC, t_WC) of 10/ 12/ 15/ 20 ns with output enable access times (t_OE) of 5/ 6/ 8/ 10 ns

are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with

multiple-bank systems.

When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume I power.

If the bus is static, then full standby power is reached (I_SB1or I_SB2). For example, the AS7C31024 is guaranteed not to exceed

0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V.

A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/ O0-

I/ O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid

bus contention, external devices should drive I/ O pins only after outputshave been disabled with output enable ( OE) or write

enable (WE).

A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.

The chips drive I/ O pins with the data word referenced by the input address. When either chip enable is inactive, output

enable is inactive, or write enable is active, output drivers stay in high-impedance mode.

Absolute maximum ratings

Parameter

Symbol

Min

–0.50

-0.50

–0.50

–

Max

+7.0

Unit

AS7C1024

Voltage on V_CCrelative to GND

AS7C31024

+5.0

Voltage on any pin relative to GND

Power dissipation

V_CC+0.50

1.0

P_D

Storage temperature (plastic)

Ambient temperature with V_CCapplied

DC current into outputs (low)

T_stg

–65

–55

–

+150

+125

°C

T_bias

I_OUT

Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect reliability.

Truth table

CE1

CE2

Data

Mode

High Z

D_OUT

Standby (I_SB, I_SB1

)

Output disable (I_CC)

Read (I_CC)

Write (_ICC)

Key: X = Don’t Care, L = Low, H = High

ALLIANCE SEMICONDUCTOR

11/ 29/ 00

123 4 5 6 7...9

中文翻译

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与AS7C31024-15JI相关器件

型号	品牌	获取价格	描述	数据表
AS7C31024-15PC	ETC	获取价格	x8 SRAM
AS7C31024-15TC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-15TI	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-15TJC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-15TJI	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-15TPC	ETC	获取价格	x8 SRAM
AS7C31024-20	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)
AS7C31024-20HC	ALSC	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32
AS7C31024-20HI	ALSC	获取价格	Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP1-32
AS7C31024-20JC	ALSC	获取价格	5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

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