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AS7C31024-15JI PDF预览

AS7C31024-15JI

更新时间: 2024-10-27 22:22:35
品牌 Logo 应用领域
ALSC 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
9页 199K
描述
5V/3.3V 128K x 8 CMOS SRAM (Evolutionary Pinout)

AS7C31024-15JI 数据手册

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AS7C1024  
AS7C31024  
®
Data retention characteristics (over the operating range)  
Parameter  
Symbol  
Test conditions  
Device  
Min  
2.0  
Max  
Unit  
V
V
CC for data retention  
VDR  
VCC = 2.0V  
AS7C1024  
5
mA  
mA  
ns  
Data retention current  
ICCDR  
CE1 VCC–0.2V or  
CE2 0.2V  
AS7C31024  
1
Chip deselect to data retention time  
Operation recovery time  
tCDR  
tR  
0
V VCC–0.2V or  
IN  
V 0.2V  
tRC  
ns  
IN  
Input leakage current  
| ILI |  
1
µA  
Data retention waveform  
Data retention mode  
V
V
V
2.0V  
V
CC  
CC  
CC  
DR  
t
t
R
CDR  
V
DR  
V
V
IH  
CE1  
IH  
AC test conditions  
– 5V output load: see Figure B or Figure C.  
– Input pulse level: GND to 3.0V. See Figure A.  
– Input rise and fall times: 2 ns. See Figure A.  
– Input and output timing reference levels: 1.5V.  
Thevenin equivalent:  
168W  
D
+1.728V (5V and 3.3V)  
OUT  
+5V  
+3.3V  
480W  
320W  
D
D
OUT  
OUT  
+3.0V  
90%  
10%  
90%  
10%  
255W  
C(14)  
GND  
255W  
C(14)  
GND  
2 ns  
Figure A: Input pulse  
GND  
Figure B: 5V Output load  
Figure C: 3.3V Output load  
Notes  
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CE1 is required to meet I specification.  
CC CC SB  
This parameter is sampled and not 100% tested.  
For test conditions, see AC Test Conditions, Figures A, B, and C.  
t
and t are specified with CL = 5pF, as in Figure C. Transition is measured ±500mV from steady-state voltage.  
CHZ  
CLZ  
This parameter is guaranteed, but not 100% tested.  
WEis High for read cycle.  
CE1 and OE are Low and CE2 is High for read cycle.  
Address valid prior to or coincident with CE1 transition Low.  
All read cycle timings are referenced from the last valid address to the first transitioning address.  
10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.  
11 All write cycle timings are referenced from the last valid address to the first transitioning address.  
12 CE1 and CE2 have identical timing.  
13 2V data retention applies to commercial temperature operating range only.  
14 C=30pF, except all high Z and low Z parameters, C=5pF.  
6
ALLIANCE SEMICONDUCTOR  
11/ 29/ 00  

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