March 2004
AS7C1024B
®
5V 128K X 8 CMOS SRAM
Features
- 300 mil SOJ
- 400 mil SOJ
- 8 × 20mm TSOP 1
- 8 x 13.4mm sTSOP 1
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• Industrial and commercial temperatures
• Organization: 131,072 words x 8 bits
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 605 mW / max @ 10 ns
• Low power consumption: STANDBY
- 55 mW / max CMOS
• 6T 0.18u CMOS technology
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
Pin arrangement
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
Logic block diagram
V
A15
CE2
WE
A13
A8
A9
A11
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CC
V
CC
9
OE
A10
GND
10
11
12
13
14
15
16
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
Input buffer
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O7
I/O0
512 x 256 x 8
Array
(1,048,576)
32-pin (8 x 20mm) TSOP I
32-pin (8 x 13.4mm) sTSOP1
A11
A9
1
OE
32
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
31
30
29
28
27
3
A8
4
A13
WE
CE2
A15
5
6
7
26
25
24
23
22
21
20
19
WE
Column decoder
8
V
CC
Control
circuit
OE
9
NC
10
11
12
13
14
15
16
A16
CE1
CE2
A14
A12
A7
A6
A1
18
17
A5
A2
A4
A3
Selection guide
-10
-15
-20
Unit
-12
Maximum address access time
10
12
15
20
ns
Maximum output enable access
time
5
6
7
8
ns
Maximum Operating Current
110
10
100
10
90
10
80
10
mA
mA
Maximum CMOS standby Current
3/26/04, v 1.2
Alliance Semiconductor
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