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AS7C1024L-15TPC PDF预览

AS7C1024L-15TPC

更新时间: 2024-11-24 20:23:59
品牌 Logo 应用领域
ALSC 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 294K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PDIP32

AS7C1024L-15TPC 数据手册

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High Performance  
128K×8  
AS7C1024  
AS7C1024L  
CMOS SRAM  
®
128K×8 CMOS SRAM  
Features  
• Easy memory expansion with CE1, CE2, OE inputs  
• Organization: 131,072 words × 8 bits  
• TTL-compatible, three-state I/O  
• 32-pin JEDEC standard packages  
- 300 mil PDIP and SOJ  
Socket compatible with 7C256 and 7C512  
- 400 mil PDIP and SOJ  
- 8 × 20 TSOP  
• ESD protection >2000 volts  
• Latch-up current > 200 mA  
• High speed  
- 10/12/15/20/25/35 ns address access time  
- 3/3/4/5/6/8 ns output enable access time  
• Low power consumption  
- Active: 770 mW max (10 ns cycle)  
- Standby:55 mW max, CMOS I/O  
11 mW max, CMOS I/O, L version  
- Very low DC component in active power  
• 2.0V data retention (L version)  
• Equal access and cycle times  
Logic block diagram  
Pin arrangement  
TSOP 8×20  
DIP, SOJ  
Vcc  
GND  
Input buffer  
NC  
A16  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
32  
Vcc  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
I/O7  
I/O6  
I/O5  
I/O4  
I/O3  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A0  
A1  
A2  
I/O7  
I/O0  
512×256×8  
A3  
A4  
A5  
A6  
A7  
A8  
Array  
8
9
(1,048,576)  
10  
11  
12  
13  
14  
15  
16  
A0  
I/O0  
I/O1  
I/O2  
GND  
WE  
OE  
CE1  
CE2  
Column decoder  
Control  
circuit  
A A A A A A A A  
9 10 1112 13 14 1516  
Selection guide  
7C1024-10 7C1024-12 7C1024-15 7C1024-20 7C1024-25 7C1024-35 Unit  
Maximum address access time  
Maximum output enable access time  
Maximum operating current  
10  
3
12  
3
15  
4
20  
5
25  
6
35  
8
ns  
ns  
140  
10.0  
2.0  
130  
10.0  
2.0  
120  
10.0  
2.0  
110  
10.0  
2.0  
100  
10.0  
2.0  
90  
mA  
mA  
mA  
10.0  
2.0  
Maximum CMOS standby current  
L
Shaded areas contain advance information.  
ALLIANCE SEMICONDUCTOR  

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