ꢀ
$6ꢁ&ꢂꢃꢄꢅ
$6ꢁ&ꢂꢃꢄꢅ/
$6ꢁ&ꢆꢂꢃꢄꢅ
$6ꢁ&ꢆꢂꢃꢄꢅ/
®
ꢂꢄꢉ.ðꢉꢀ&026ꢀ65$0ꢀꢊ&RPPRQꢀ,ꢋ2ꢌꢀIDPLO\
)HDWXUHV
• Organization: 131,072 words × 8 bits
• High speed
- 10/ 12/ 15/ 20 ns address access time
- 3/ 3/ 4/ 5 ns output enable access time
• Low power consumption available
- Active: 180 mW max (3V, 15 ns)
- Standby: 1.8 mW max, CMOS I/ O
- Very low DC component in active power
• 2.0V data retention
• TTL/ LVTTL-compatible, three-state I/ O
• 32-pin JEDEC standard packages
- 300 mil PDIP and SOJ
Socket compatible with 7C512 (64K×8)
- 400 mil SOJ
- 8mm × 20mm TSOP
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 3.3V and 5.0V versions available
• Industrial and commercial temperature available
• Equal access and cycle times
• Easy memory expansion with CE1, CE2, OE inputs
• Intelliwatttm low power and CPG versions available
/RJLFꢀEORFNꢀGLDJUDP
3LQꢀDUUDQJHPHQW
TSOP
DIP, SOJ
Vcc
GND
A11
A9
1
OE
Input buffer
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A15
CE2
NC
A16
A14
A12
A7
1
32
2
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
3
A8
3
4
A13
WE
CE2
A15
A0
A1
A2
4
5
WE
6
5
I/O7
I/O0
A13
7
A6
6
A8
8
512×256×8
Vcc
NC
A16
A14
A12
A7
A5
7
A9
A3
9
A11
A4
8
A4
A5
A6
A7
A8
10
11
12
13
14
15
16
Array
A3
9
OE
A10
A2
10
11
12
13
14
15
16
(1,048,576)
A1
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A6
A1
I/O0
I/O1
I/O2
GND
A5
A2
A4
A3
WE
OE
CE1
CE2
Column decoder
Control
circuit
6HOHFWLRQꢀJXLGH
-10
-12
12
-15
-20
20
5
Unit
ns
Maximum address access time
10
3
15
4
Maximum output enable access time
3
ns
AS7C1024
175
–
160
120
100
60
120
95
70
50
0.1
110
80
65
45
0.1
mA
mA
mA
mA
mA
AS7C1024L
AS7C31024
AS7C31024L
Maximum operating current
150
–
Maximum static standby current (L)
0.1
0.1
Shaded areas contain advance information.
$//,$1&(ꢀ6(0,&21'8&725
ꢇꢈ
Copyright ©1998 Alliance Semiconductor. All rights reserved.
Powered by ICminer.com Electronic-Library Service CopyRight 2003