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AS4C16M16S-7TCN PDF预览

AS4C16M16S-7TCN

更新时间： 2024-02-26 16:02:17
品牌 Logo 应用领域
ALLIED 时钟动态存储器ISM频段光电二极管内存集成电路
页数 文件大小 规格书
55页 1954K
描述
16MX16 SYNCHRONOUS DRAM, 5.4ns, PDSO54, 0.400 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSOPII-54

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AS4C16M16S-7TCN 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：TSOP2包装说明：0.400 INCH, HALOGEN FREE AND ROHS COMPLIANT, PLASTIC, TSOPII-54
针数：54Reach Compliance Code：compliant
风险等级：5.66访问模式：FOUR BANK PAGE BURST
最长访问时间：5.4 ns其他特性：AUTO/SELF REFRESH
JESD-30 代码：R-PDSO-G54长度：22.22 mm
内存密度：268435456 bit内存集成电路类型：SYNCHRONOUS DRAM
内存宽度：16功能数量：1
端口数量：1端子数量：54
字数：16777216 words字数代码：16000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16MX16
封装主体材料：PLASTIC/EPOXY封装代码：TSOP2
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.8 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：10.16 mmBase Number Matches：1

AS4C16M16S-7TCN 数据手册

 浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第3页浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第4页浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第5页浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第7页浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第8页浏览型号AS4C16M16S-7TCN的Datasheet PDF文件第9页 
FEBRUARY 2011  
AS4C16M16S  
256Mb / 16M x 16 bit Synchronous DRAM (SDRAM)  
Commands  
1
BankActivate  
(RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A12 = Row Address)  
The BankActivate command activates the idle bank designated by the BA0, 1 signal. By latching the row  
address on A0 to A12 at the time of this command, the selected row access is initiated. The read or write  
operation in the same bank can occur after a time delay of tRCD (min.)  
from the time of bank activation. A  
subsequent BankActivate command to a different row in the same bank can only be issued after the previous  
active row has been precharged (refer to the following figure). The minimum time interval between successive  
is defined by tRC (min.). The SDRAM has four internal banks on  
BankActivate commands to the same bank  
the same chip and shares part of the  
internal circuitry to reduce chip area; therefore it restricts the back-to-  
banks. tRRD (min.) specifies the minimum time required between activating different  
back activation of the two  
banks. After this  
command is used, the Write command and the Block Write command perform the no mask  
write operation.  
2
BankPrecharge command  
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Bank, A10 = "L", A0-A9, A11 and A12 = Don't care)  
The BankPrecharge command precharges the bank designated by BA signal. The precharged bank is  
tRAS(min.) is  
switched from the active state to the idle state. This command can be asserted anytime after  
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is  
specified by t RAS(max.). Therefore, the precharge function must be performed in any active bank within t  
RAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated  
again.  
3
4
PrechargeAll command  
(RAS# = "L", CAS# = "H", WE# = "L", BAs = Don‟t care, A10 = "H", A0-A9, A11 and A12 = Don't care)  
The PrechargeAll command precharges all banks simultaneously and can be issued even if all banks are  
not in the active state. All banks are then switched to the idle state.  
Read command  
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "L", A0-A8 = Column Address)  
row in an  
The Read command is used to read a burst of data on consecutive clock cycles from an active  
active bank. The bank must be active for at least tRCD (min.) before the Read command is issued. During read  
bursts,  
the valid data-out element from the starting column address will be available following the CAS#  
latency after the issue of the Read command. Each subsequent data-out element will be valid by the next  
positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst  
unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by  
the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of  
the page it will wrap to column 0 and continue).  
6
1...3456789...55

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