FEBRUARY 2011
AS4C16M16S
256Mb / 16M x 16 bit Synchronous DRAM (SDRAM)
Pin Descriptions
Table 3. Pin Details of AS4C16M16S
Symbol
Type
Description
CLK
Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the
positive edge of CLK. CLK also increments the internal burst counter and controls the output
registers.
CKE
Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If CKE goes low
synchronously with clock (set-up and hold time same as other inputs), the internal clock is
suspended from the next clock cycle and the state of output and burst address is frozen as long
as the CKE remains low. When all banks are in the idle state, deactivating t he clock controls
the entry to the Power Down and Self Refresh modes. CKE is synchronous except after the
device enters Power Down and Self Refresh modes, where CKE becomes asynchronous until
exiting the same mode. The input buffers, including CLK, are disabled during Power Down and
Self Refresh modes, providing low standby power.
BA0,BA1
Input Bank Activate: BA0, BA1 input select the bank for operation.
BA1
0
BA0
0
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
0
1
1
0
1
1
A0-A12
Input Address Inputs: A0-A12 are sampled during the BankActivate command (row address A0-
A12) and Read/Write command (column address A0-A8 with A10 defining Auto Precharge) to
select one location out of the 4M available in the respective bank. During a Precharge command,
A10 is sampled to determine if all banks are to be precharged (A10 = HIGH).
inputs also provide the op-code during a Mode Register Set command.
The address
CS#
Input Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external
bank selection on systems with multiple banks. It is considered part of the command code.
RAS#
Input Row Address Strobe: The RAS# signal defines the operation commands in conjunction with
the CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS#
are asserted "LOW" and CAS# is asserted "HIGH," either the BankActivate command or t he
Precharge command is selected by the WE# signal. When the WE# is asserted "HIGH," the
BankActivate command is selected and the bank designated by BA is turned on to the active
state. When the WE# is asserted "LOW," the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
CAS#
WE#
Input Column Address Strobe: The CAS# signal defines the operation commands in conjunction with
the RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held
"HIGH" and CS# is asserted "LOW," the column access is started by asserting CAS# "LOW."
Then, the Read or Write command is selected by asserting WE# "LOW" or "HIGH."
Input Write Enable: The WE# signal defines the operation commands in conjunction with the RAS#
and CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select
the BankActivate or Precharge command and Read or Write command.
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