AS4C1M16E5
®
5V 1M×16 CMOS DRAM (EDO)
Features
• 1024 refresh cycles, 16 ms refresh interval
• Organization: 1,048,576 words × 16 bits
- RAS-only or CAS-before-RAS refresh Read-modify-write
• TTL-compatible, three-state DQ
• JEDEC standard package and pinout
- 400 mil, 42-pin SOJ
• High speed
- 45/50/60 ns RAS access time
- 20/20/25 ns hyper page cycle time
- 10/12/15 ns CAS access time
• Low power consumption
- Active: 740 mW max (AS4C1M16E5-60)
- Standby: 5.5 mW max, CMOS DQ
• Extended data out
- 400 mil, 44/50-pin TSOP II
• 5V power supply (AS4C1M16E5)
• 3V power supply (AS4LC1M16E5)
• Industrial and commercial temperature available
Pin designation
Pin arrangement
Pin(s)
A0 to A9
RAS
Description
TSOP II
SOJ
VCC
DQ1
DQ2
DQ3
DQ4
VCC
VSS
1
2
3
4
5
6
7
8
50
49
48
47
46
45
44
43
42
41
40
Address inputs
Vcc
DQ1
DQ2
DQ3
DQ4
Vcc
DQ5
DQ6
DQ7
DQ8
NC
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VSS
DQ16
DQ15
DQ14
DQ13
VSS
DQ12
DQ11
DQ10
DQ9
2
DQ16
DQ15
DQ14
DQ13
VSS
Row address strobe
Input/output
3
4
5
DQ1 to DQ16
OE
6
DQ5
7
DQ12
DQ11
DQ10
DQ9
NC
Output enable
8
DQ6
DQ7
DQ8
9
9
WE
Write enable
10
11
12
13
14
15
16
17
18
19
20
21
10
11
NC
NC
NC
WE
LCAS
UCAS
OE
UCAS
LCAS
Column address strobe, upper byte
Column address strobe, lower byte
Power
RAS
NC
A9
NC
A8
NC
NC
WE
RAS
NC
NC
A0
15
16
17
18
19
20
21
22
36
35
34
33
32
31
30
29
NC
LCAS
UCAS
OE
A9
A8
VCC
A0
A7
A1
A6
A2
A5
VSS
Ground
A3
A4
Vcc
VSS
A7
A6
A1
A2
A3
VCC
23
24
25
A5
A4
VSS
28
27
26
Selection guide
Symbol
tRAC
tAA
-45
45
-50
50
-60
60
Unit
ns
Maximum RAS access time
Maximum column address access time
Maximum CAS access time
23
25
30
ns
tCAC
tOEA
tRC
10
12
15
ns
Maximum output enable (OE) access time
Minimum read or write cycle time
Minimum hyper page mode cycle time
Maximum operating current
12
13
15
ns
75
80
100
25
ns
tHPC
ICC1
ICC5
20
20
ns
155
1.0
145
1.0
135
1.0
mA
mA
Maximum CMOS standby current
4/11/01; v.1.0
Alliance Semiconductor
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