Datasheet > 存储 > DRAM> AS4C14405-70TC

AS4C14405-70TC

更新时间： 2024-02-15 15:57:47

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
16页	395K
描述
1M-bit × 4 CMOS DRAM (Fast page mode or EDO)

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AS4C14405-70TC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	TSOP, TSOP20/26(UNSPEC)	Reach Compliance Code：	unknown
风险等级：	5.92	最长访问时间：	70 ns
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G20
JESD-609代码：	e0	内存密度：	4194304 bit
内存集成电路类型：	EDO DRAM	内存宽度：	4
端子数量：	20	字数：	1048576 words
字数代码：	1000000	最高工作温度：	70 °C
最低工作温度：		组织：	1MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP	封装等效代码：	TSOP20/26(UNSPEC)
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	5 V	认证状态：	Not Qualified
刷新周期：	1024	自我刷新：	NO
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.06 mA	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子位置：	DUAL
Base Number Matches：	1

AS4C14405-70TC 数据手册

AS4C14400

Notes

I_CC1, I_CC3, I_CC4, and I_CC6depend on cycle rate.

I_CC1and I_CC4depend on output loading. Specified values are obtained with the output open.

An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal

refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

extended periods of bias without clocks (greater than 16 ms).

AC Characteristics assume t_T= 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, V_IL(min) ≥ GND and V_IH

(max) ≤ V_CC. See AC test conditions for more information.

V_IH(min) and V_IL(max) are reference levels for measuring timing of input signals. Transition times are measured between V_IHand V_IL.

Operation within the t_RCD(max) limit ensures that t_RAC(max) can be met. t_RCD(max) is specified as a reference point only. If t_RCDis greater than the

specified t_RCD(max) limit, then access time is controlled exclusively by t_CAC

Operation within the t_RAD(max) limit ensures that t_RAC(max) can be met. t_RAD(max) is specified as a reference point only. If t_RADis greater than the

specified t_RAD(max) limit, then access time is controlled exclusively by t_AA

Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).

Either t_RCHor t_RRHmust be satisfied for a read cycle.

10 t_OFF(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.

11 t_WCS, t_WCH, t_RWD, t_CWDand t_AWDare not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If t_WCS

≥

t_WCS(min) and t_WCH≥ t_WCH(min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle.

If t_RWD≥ t_RWD(min), t_CWD≥ t_CWD(min) and t_AWD≥ t_AWD(min), the cycle is a read-write cycle and the data out will contain data read from the

selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.

13 Access time is determined by the longest of t_CAAor t_CACor t_CAP

14 t_ASC≥ t_CPto achieve t_PC(min) and t_CAP(max) values.

15 These parameters are sampled and not 100% tested.

AC test conditions

- Access times are measured with output reference

+5V

levels of V = 2V and V = 0.8 V

- Input rise and fall times: 5 ns

R1 = 828W

out

+3.0V

90%

10%

100 pF*

R2 = 295W

GND

*including scope

and jig capacitance

10%

Figure A: Input waveform

Figure B: Equivalent output load

Key to switching waveforms

Don’t care input

Rising input

Falling input

Undefined output

1...4 5 678 9 10...16

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