Datasheet > AS1160

AS1160

更新时间： 2022-10-11 11:45:13

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
29页	902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

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AS1160 数据手册

AS1160/AS1161

Datasheet - Electrical Characteristics

Table 7. Electrical Characteristics (Continued)

Symbol

Parameter

Conditions

Min

Typ

-30

3.0

Max Unit

Input Current, TMS, TDI,

TRSTN inputs

IILR

VIN = 0V

-60

µA

VOH

VOL

High Level Output Voltage

Low Level Output Voltage

IOH = -4 mA

IOH = 4 mA

2.2

VDD

0.5

GND 0.25

Output Short Circuit

Current

IOS

IOZ

VOUT = 0V

-15

-80

-1

-35

-60

µA

Output Short Circuit

Current, TDO output

-150 -220

PWDNN or REN = 0V,

VOUT = 0V or VDD

Tri-State Output Current

Deserializer Supply Current (pins DVDD and AVDD)

f = 20MHz

f = 66MHz

Deserializer Supply

ICCR

Figure 17 on page 12

Current (Worst Case)

100

130

Deserializer Supply

Current (Powerdown)

ICCXR

PWDNN = 0V, REN = 0V

0.75

1.0

Deserializer Timing Requirements for REFCLK

Table 8. Deserializer Timing Requirements for REFCLK

Symbol

fRFCLK

tRFCP

Parameter

Conditions

Min

Typ

Max

Unit

MHz

REFCLK Frequency

REFCLK Period

15.15

tRFDC

REFCLK Duty Cycle

REFCLK-to-TCLK Ratio

REFCLK Transition Time

tRFCP/tTCP

tRFTT

105

Deserializer Switching Characteristics

Table 9. Deserializer Switching Characteristics¹

Pin/

Symbol

tRCP

Parameter

Conditions

Min

Typ

Max

Unit

Frequency

Receiver Out Clock

Period

tRCP = tTCP,

Figure 26 on page 15

RCLK

15.15

CMOS/TTL Low-to-

High Transition Time

tCLH

1.5

1.4

RCLK,

ROUTx,

LOCKN

Figure 19 on page 13

CMOS/TTL High-to-

Low Transition Time

tCHL

All temperatures, all

frequencies

1.6 x tRCP

+ 1.0

1.75 x tRCP

+ 7.0

Deserializer Delay,

Figure 27 on page 16

1.6 x tRCP 1.6 x tRCP 1.6 x tRCP

+ 2.0 + 4.0 + 6.0

tDD

Room temperature, 3.3V

20MHz

66MHz

1.75 x tRCP 1.75 x tRCP 1.75 x tRCP

+ 2.0 + 4.0 + 6.0

20MHz

66MHz

20MHz

0.4 x tRCP 0.5 x tRCP

0.38 x tRCP 0.5 x tRCP

-0.4 x tRCP 0.5 x tRCP

ROUT Data Valid

tROS

tROH

Figure 28 on page 16

Before RCLK Time

ROUT Data Valid After

RCLK Time

-0.38 x

-0.5 x tRCP

tRCP

66MHz

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