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AS1160 PDF预览

AS1160

更新时间: 2022-10-11 11:45:13
品牌 Logo 应用领域
艾迈斯 - AMSCO /
页数 文件大小 规格书
29页 902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

AS1160 数据手册

 浏览型号AS1160的Datasheet PDF文件第4页浏览型号AS1160的Datasheet PDF文件第5页浏览型号AS1160的Datasheet PDF文件第6页浏览型号AS1160的Datasheet PDF文件第8页浏览型号AS1160的Datasheet PDF文件第9页浏览型号AS1160的Datasheet PDF文件第10页 
AS1160/AS1161  
Datasheet - Electrical Characteristics  
Table 6. Serializer Switching Characteristics1  
Symbol  
tDIS  
Parameter  
Conditions  
Min  
0
Typ  
Max  
Unit  
ns  
DINx Setup to TCLK Time  
DINx Hold from TCLK Time  
Figure 21 on page 13  
tDIH  
4
ns  
DO+, DO- High-to-  
Tri-State Delay  
tHZD  
tLZD  
tZHD  
tZLD  
tPWDL  
tSPW  
tPLD  
tSD  
1.5  
1.5  
1.5  
1.5  
5
5
5
5
ns  
ns  
ns  
ns  
µs  
ns  
ns  
ns  
DO+, DO- Low-to-  
Tri-State Delay  
Figure 22 on page 14 2  
DO+, DO- Tri-State-to-  
High Delay  
DO+, DO- Tri-State-to-  
Low Delay  
PWDNN minimum low time  
after VDD is in regulation  
Figure 23 on page 14  
Figure 25 on page 15  
Figure 24 on page 14  
Figure 26 on page 15  
50  
5 x  
tTCP  
SYNC Pulse Width  
Serializer PLL Lock Time  
Serializer Delay  
400 x  
tTCP  
tTCP/2 tTCP/2  
+ 3  
tTCP/2  
+ 5  
ps  
(pp)  
f = 20MHz  
150  
300  
Deterministic Jitter (p-p)  
(Worst Case) ICC-Pattern  
tDJIT  
tRJIT  
Figure 32 on page 18  
ps  
(pp)  
f = 66MHz  
50  
100  
f = 20MHz  
f = 66MHz  
25  
8
45  
15  
Random Jitter  
(Worst Case) ICC-Pattern  
ps  
(RMS)  
1. Guaranteed by simulation and characterization.  
2. Because the serializer is in tri-state mode, the deserializer will lose PLL lock and have to resynchronize before  
data transfer.  
Deserializer Electrical Characteristics  
AVDD = DVDD = 3V to 3.6V, TAMB = -40°C to +85°C, RLOAD=28Ω, CLOAD = 15pF, Receiver Input Range: 0V to 2.4V,  
typical values @ TAMB = +25°C and VDD = 3.3V (unless otherwise specified).  
Table 7. Electrical Characteristics  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
Deserializer Bus LVDS DC Specifications (pins RI+ and RI-)  
Differential Threshold High  
VTH  
+10  
-20  
+75  
mv  
Voltage  
VCM = +1.2V  
Differential Threshold Low  
Voltage  
VTL  
IIN  
-75  
VIN = 2.4V, VDD = 3.6V or 0V  
VIN = 0V, VDD = 3.6V or 0V  
-1  
-1  
+1  
µA  
+1  
Input Current  
Deserializer LVCMOS/LVTTL DC Specifications (input pins PWDNN, RCKR/FN, REN, REFCLK; output pins  
ROUT0:ROUT9, RCLK, LOCKN)  
VIH  
VIL  
IIN  
High Level Input Voltage  
Low Level Input Voltage  
Input Current  
2.0  
GND  
-1  
VDD  
0.8  
+1  
V
V
VIN = 0V or 3.6V  
µA  
www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61  
Revision 1.01  
7 - 29  

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