Datasheet > AS1160

AS1160

更新时间： 2022-10-11 11:45:13

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
29页	902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

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AS1160 数据手册

AS1160/AS1161

Datasheet - Pinout

Figure 3. AS1161 Pin Assignments (Top View)

DGND N/C REFCLK AGND ROUT1 DGND DVDD

B1 B2 B3 B4 B5 B6 B7

AVDD AGNDRCKR/FNROUT2 DGND ROUT3 DVDD

RI-

AVDD

N/C ROUT0 DVDD DVDD ROUT4

D3 D4 D5 D6 D7

DVDD ROUT5 DGND

E5 E6 E7

N/C DGND TCK TRSTN DGND

F3 F4 F5 F6 F7

AVDD AVDD AGND AGND ROUT8 TDI ROUT6

REN

RI+ PWDNN N/C

E2 E3 E4

LOCKN RCLK

F1 F2

AVDD AGND DGND ROUT9 ROUT7 TDO

TMS

Table 2. AS1161 Pin Descriptions

Pin Number

Pin Name

Description

Data Output. ±4mA CMOS level outputs.

ROUT0:ROUT9

Recovered Clock Rising/Falling Strobe Select. LVTTL level input. Selects RCLK

active edge for strobing of ROUT0:ROUT9 data.

1 = Rising edge.

RCKR/FN

0 = Falling edge.

Reference Clock Input. LVTTL level input. Input for 20MHz - 66MHz system clock.

+ Serial Data Input. Non-inverting Bus LVDS differential input.

- Serial Data Input. Inverting Bus LVDS differential input.

REFCLK

RI+

RI-

Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states

the outputs and puts the device into low power sleep mode.

Lock. CMOS level output. This signal goes low when the deserializer PLL locks onto

the embedded clock edge.

Recovered Clock. CMOS level output. Parallel data rate clock recovered from

embedded clock. Used to strobe ROUT0:ROUT9.

PWDNN

LOCKN

RCLK

Output Enable. LVTTL level input. If REN is set to logic low ROUT0:ROUT9 and RCLK

are in tri-state condition.

See Figure 3

REN

+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital

circuitry.

DVDD

DGND

Digital Circuit Ground

+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD

should be at the same potential and must not be more than 0.3V apart even on

transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.

AVDD

Analog Ground (PLL and Analog Circuits).

IEEE 1149.1 Test Data Input

AGND

TDI

IEEE 1149.1 Test Data Output

TDO

TMS

TCK

IEEE 1149.1 Test Mode Select Input

IEEE 1149.1 Test Clock Input

IEEE 1149.1 Test Reset Input

TRSTN

N/C

No Connection. Leave open-circuit, do not connect these pins.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

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