Datasheet > AS1160

AS1160

更新时间： 2022-10-11 11:45:13

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
29页	902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

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AS1160 数据手册

AS1160/AS1161

Datasheet - Pinout

4 Pinout

Pin Assignments and Descriptions

Figure 2. AS1160 Pin Assignments (Top View)

DGND N/C

DIN0 SYNC1 AVDD AVDD

N/C

B3 B4 B5 B6

DIN1

N/C SYNC2 AVDD AGND AGND AVDD

C2 C3 C4 C5 C6 C7

N/C AGND PWDNN

DIN3 DGND DVDD DVDD

DIN5

DIN2

DIN4

N/C

DO-

DEN

DO+

DIN7

DIN6

TMS TCLK DVDD DGND AGND

TDI

DIN8

TCK

DIN9 DGND N/C

AGND

TCKR/FN

TDO TRSTN

DGND AVDD

N/C

Table 1. AS1160 Pin Descriptions

Pin Number

Pin Name

Description

Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input

DIN0:DIN9

Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK

active edge for strobing of DINx data.

1 = Rising edge.

TCKR/FN

0 = Falling edge.

+ Serial Data Output. Non-inverting Bus LVDS differential output.

- Serial Data Output. Inverting Bus LVDS differential output.

DO+

DO-

Serial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS

outputs are in tri-state condition.

DEN

Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the

outputs and puts the device into low power sleep mode.

PWDNN

TCLK

Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock.

Synchronization. LVTTL level input. Assertion of SYNC (high) for at least 5 clock

cycles to be transmit a synchronization signal (SYNCPAT) on the Bus LVDS serial

output. Synchronization symbols continue to be sent if SYNCx continues to be

asserted. SYNC1 and SYNC2 pins are combined through an OR gate.

SYNC1,

SYNC2

See Figure 2

+3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry.

Digital Circuit Ground. GND reference point for the digital part of the AS1160.

DVDD

DGND

+3.0V to +3.6V Analog Power Supply (PLL and Analog Circuits). AVDD and DVDD

should be at the same potential and must not be more than 0.3V apart even on

transient basis. Both supplys should be decoupled by a capacitor of typically 10nF.

AVDD

Analog Ground (PLL and Analog Circuits).

IEEE 1149.1 Test Data Input

AGND

TDI

IEEE 1149.1 Test Data Output

TDO

TMS

TCK

IEEE 1149.1 Test Mode Select Input

IEEE 1149.1 Test Clock Input

IEEE 1149.1 Test Reset Input

TRSTN

N/C

No Connection. Leave open-circuit, do not connect these pins.

www.austriamicrosystems.com/Interfaces-LVDS/AS1160_61

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