Datasheet > AS1160

AS1160

更新时间： 2022-10-11 11:45:13

品牌	Logo	应用领域
艾迈斯 - AMSCO		/
页数	文件大小	规格书
29页	902K
描述
20MHz - 66MHz, 10-Bit Bus, IEEE 1149.1 (JTAG) Compliant LVDS Serializer/Deserializer

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AS1160 数据手册

AS1160/AS1161

Datasheet - Electrical Characteristics

6 Electrical Characteristics

AVDD = DVDD = 3V to 3.6V, TAMB = -40°C to +85°C, RLOAD=28Ω, CLOAD = 10pF, typical values @ TAMB = +25°C and

VDD = 3.3V (unless otherwise specified).

Serializer Electrical Characteristics

Table 4. Electrical Characteristics

Symbol

Parameter

Conditions

Min

Typ

Max Unit

Serializer LVCMOS/LVTTL DC Specifications (pins DINx, TCLK, PWDNN, TCKR/FN, SYNC1, SYNC2, DEN)

VIH

VIL

IIN

High Level Input Voltage

Low Level Input Voltage

Input Current

2.0

GND

-1

VDD

0.8

VIN = 0V or 3.6V

µA

Serializer Bus LVDS DC Specifications (pins DO+ and DO-)

Output Differential Voltage

VOD

Figure 34 on page 18

200

1.1

360

(DO+ to DO-)

Output Differential Voltage

Unbalance

ΔVOD

VOS

Offset Voltage

1.2

1.3

ΔVOS

Offset Voltage Unbalance

Output Short-Circuit

Current

DO = 0V, DIN = High,

IOS

IOZ

IOX

-13

-20

µA

PWDNN and DEN = VDD

Tri-State Output Current

PWDNN or DEN = GND, DO = 0V or VDD

-1

PWDNN = DEN = VDD = 0V,

DO = 0V or 3.6V

Power-Off Output Current

Serializer Supply Current (pins DVDD and AVDD)

f = 20MHz

f = 66MHz

Serializer Supply Current

ICCD

Figure 16 on page 12

µA

(Worst Case) ICC-Pattern

Serializer Supply Current

(Powerdown)

ICCXD

PWDNN = GND, fCLK = DC (off)

400

700

Serializer Timing Requirements for TCLK

Table 5. Serializer Timing Requirements for TCLK

Symbol

fCLK

Parameter

Conditions

Min

Typ

Max

Unit

MHz

Transmit Clock Freq.

tTCP

Transmit Clock Period

Transmit Clock Duty Cycle

TCLK Input Transition Time

15.15

Figure 20 on page 13

tTCDC

tCLKT

(RMS)

tJIT

TCLK Input Jitter

150

Serializer Switching Characteristics

Table 6. Serializer Switching Characteristics¹

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Bus LVDS Low-to-High

Transition Time

tLLHT

0.25

0.4

Figure 18 on page 13

Bus LVDS High-to-Low

Transition Time

tLHLT

0.25

0.4

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