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AN113

更新时间： 2024-10-29 03:18:47

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SERIAL COMMUNICATION WITH THE SMBUS

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AN113

SERIAL COMMUNICATION WITH THE SMBUS

nizes its own address and responds, it becomes the

slave device for that transfer. It is important to note

that assigning one specified master device is not

necessary. Any device may assume the role of mas-

ter or slave for any particular transfer. In the case

that two devices attempt to initiate a transfer simul-

taneously, an arbitration scheme forces one device

to give up the bus. This arbitration scheme is non-

destructive (one device wins and no information is

lost). Arbitration is discussed in depth in the arbi-

tration section.

Relevant Devices

This application note applies to the following

devices:

C8051F000, C8051F001, C8051F002,

C8051F005, C8051F006, C8051F010, C8051F011,

C8051F012, C8051F020, C8051F021,

C8051F022, and C8051F023.

Introduction

Two wires are used in SMBus communication:

SDA (serial data), and SCL (serial clock). Each

line is bi-directional, with direction depending on

what modes the devices are in. The master always

supplies SCL; either device may transmit on SDA.

Both lines should be connected to a positive power

supply through a pull-up circuit. All devices on the

SMBus line should have an open-drain or open col-

lector output, so that the lines may remain high

when the bus is free. The line is pulled low if one or

more devices attempts to output a LOW signal. All

devices must output a HIGH for the line to stay

high. A typical SMBus configuration is shown in

Figure 1 on page 2.

C8051F0xx devices are equipped with an SMBus

serial I/O device that is compliant with the System

Management Bus Specification version 1.1, as well

as the I C serial bus. The SMBus is a bi-direc-

tional, 2-wire interface capable of communication

with multiple devices. SMBus is a trademark of

Intel; I C is a trademark of Philips Semiconductor.

This application note describes configuration and

operation of the SMBus. Example assembly and C

code is given: (1) Interfacing a single EEPROM

with 1-byte address space, in assembly; (2) Inter-

facing multiple EEPROMs with 2-byte address

space, in C; and (3) Peer-to-peer communication

between two C8051F0xx devices, in C.

SMBus Specification

This section presents a description of the SMBus

protocol. The SMBus discussion begins in the next

section--Using the SMBus.

SMBus Structure

An SMBus system is a 2-wire network, where each

device has a unique address and may be addressed

by any other device on the network. All transfers

are initiated by a master device; if a device recog-

Rev. 1.3 12/03

AN113-DS13

12 3 4 5 6 7...52

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