AN105
FETs As VoltageĆControlled Resistors
Introduction: The Nature of VCRs
A voltage-controlled resistor (VCR) may be defined as a Figure 1 details typical operating characteristics of an n-
three-terminal variable resistor where the resistance val- channel JFET. Most amplification or switching operations
ue between two of the terminals is controlled by a voltage of FETs occur in the constant-current (saturated) region,
potential applied to the third.
shown as Region II. A close inspection of Region I (the un-
saturated or pre-pinchoff area) reveals that the effective
slope indicative of conductance across the channel from
drain-to-source is different for each value of gate-source
bias voltage. The slope is relatively constant over a range of
applied drain voltages, so long as the gate voltage is also
constant and the drain voltage is low.
For a junction field-effect transistor (JFET) under certain
operating conditions, the resistance of the drain-source
channel is a function of the gate-source voltage alone and
the JFET will behave as an almost pure ohmic resistor.
Maximum drain-source current, I , and minimum re-
DSS
sistance r , will exist when the gate-source voltage
DS(on)
is equal to zero volts (V = 0). If the gate voltage is in-
GS
creased (negatively for n-channel JFETs and positively
for p-channel), the resistance will also increase. When the
drain current is reduced to a point where the FET is no
longer conductive, the maximum resistance is reached.
The voltage at this point is referred to as the pinchoff or
Resistance Properties of FETs
The unique resistance-controlling properties of FETs can
be deduced from Figure 2, which is an expanded-scale
plot of the encircled area in the lower left-hand corner of
Figure 1. The output characteristics all pass through the
origin, near which they become almost straight lines so
cutoff voltage and is symbolized by V = V
. Thus
GS
GS(off)
the device functions as a voltage- controlled resistor.
that the incremental value of channel resistance, r , is
DS
essentially the same as that of dc resistance, r , and is a
DS
Locus Curve
V
DS
= V - V
GS GS(off)
function of V
GS.
Region 1
Ohmic Region
Region 2
V
= 0
GS
I
DSS
Figure 2 shows an extension of the operating characteris-
tics into the third quadrant for a typical n-channel JFET.
While such devices are normally operated with a positive
Current Saturation Region
drain-source voltage, small negative values of V are
possible. This is because the gate-channel PN junction
must be slightly forward-biased before any significant
DS
V
GS
t 0
amount of gate current flows. The slope of the V bias
GS
line is equal to I /V = 1/r . This value is controlled
D
DS
DS
V
GS
→ V
GS(off)
by the amount of voltage applied to the gate. Minimum
, usually expressed as r , occurs at V = 0 and
V
P
r
DS
DS(on)
GS
is dictated by the geometry of the FET. A device with a
channel of small cross-sectional area will exhibit a high
V
DS
- DrainĆSource Voltage (V)
r
and a low I . Thus a FET with high I
should
DSS
DS(on)
DSS
Figure 1. Typical NĆChannel JFET
Operating Characteristics
be chosen where design requirements indicate the need
for a low r
.
DS(on)
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Siliconix
1
10-Mar-97