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Designing a Superheterodyne Receiver Using an IF Sam pling Diversity Chipset
by Brad Brannon
Abstract: The paper introduces a chipset to sim plify re-
ceiver design and puts forth a design exam ple based on
GSM but can be extended to m any open or closed air
interface. Advances in analog converter technology
now allow IF sam pling which can greatly sim plify re-
ceiver design. Advances in digital integrated circuits
also advance the state of the art in term s of digital tun-
ing and filtering. Together these two chips can replace
m any of the cum bersom e stages of a traditional analog
receiver with predictable and reliable perform ance.
sacrificing perform ance? Perhaps the real question is
can perform ance be enhanced. One solution is to digi-
tize the analog signals and do the processing in a DSP.
Once in the digital dom ain, m any creative and propri-
etary processes can take place to enhance and add
value, while elim inating m any of the m anufacturing
problem s (alignm ent and com ponent yield) that often
increase the cost of m anufacturing and reduce m argins.
Already, it is com m on practice to use an analog-to-
digital converter to form the detector and a DSP (digital
signal processor) to process the data. However, this
does not reduce the cost or com plexity of the design (to
digitize the baseband), it sim ply adds flexibility. What is
needed is an analog to digital converter that can digitize
closer to the antenna. Sam pling at the antenna is not
realistic since som e am ount of band select and filtering
m ust occur prior to the ADC to m inim ize adjacent chan-
nel issues. However, sam pling at the first IF is practical.
The superheterodyne receiver is still a workhorse in re-
ceiver technology. It has served its duty faithfully for
m any years now. However new technologies in receiver
com ponent designs are offering to extend the possibili-
ties into the digital age.
A typical receiver design m ay consist of two or three
down conversions to provide the sensitivity and selec-
tivity required of the individual receiver. With each
down conversion, a local oscillator, m ixer and filter are
required. Each additional stage adds com plexity, cost
and difficulty of m anufacture.
FILTER &
LNA
FILTER &
LNA
ADC
DSP
LO
FILTER
&
LNA
FILTER
&
LNA
FILTER
&
LNA
DETECTOR
PROCESS
Figure 2. Digital Receiver Block Diagram
IF SAMPLING
LO
LO
LO
Recent advances in converter technology have allowed
data converters to faithfully sam ple analog signals as
high as several hundred MHz. Sam ple rates need only
be as high as twice the signal bandwidth to keep the
Nyquist principle. Since m ost air interface standards
are less than a few MHz wide, sam ple rates in the tens of
MHz are required, elim inating the need for extrem ely
fast sam ple rates in radio design. Thus allowing for low
cost digitizers.
Figure 1. Typical Receiver Block Diagram
As shown above in the block diagram , receiver technol-
ogy can be “straight forward”, however, im plem enta-
tion and m anufacture can be another story.
There are several key issues that m ust be addressed. Of
course, the issues of noise and intercept point are al-
ways of concern when it com es to receiver design.
However, in m oderate and high volum e applications,
questions about assem bly and test begin to arise. It is
one thing to build one in the lab, but it is a com pletely
different story to build m any in production. With three
local oscillators, m ixers and IF strips, alignm ent can be
a real issue, even with autom ated tools. To keep
m anufacturing cost low, several of these analog stages
m ust be elim inated, but how can this be done without
One such analog to digital converter (ADC) that per-
form s this function is the AD6600. The AD6600 can
digitize up to 20 MSPS and sam ple analog signals up to
250 MHz with 60 dB spurious free dynam ic range. In ad-
dition to high perform ance data conversion, this ADC
also includes gain control and dual inputs to facilitate
diversity applications.
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