Datasheet > AM79C850KCW

AM79C850KCW

更新时间： 2024-10-29 08:28:27

品牌	Logo	应用领域
超微 - AMD		外围集成电路数据传输时钟
页数	文件大小	规格书
97页	331K
描述
SUPERNET-R 3

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技术参数
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AM79C850KCW 技术参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	FQFP,	针数：	208
Reach Compliance Code：	unknown	HTS代码：	8542.31.00.01
Is Samacsys：	N	地址总线宽度：	8
边界扫描：	YES	最大时钟频率：	12.5 MHz
数据编码/解码方法：	NRZI	最大数据传输速率：	12.5 MBps
外部数据总线宽度：	16	JESD-30 代码：	S-PQFP-G208
长度：	28 mm	低功率模式：	NO
DMA 通道数量：	1	I/O 线路数量：
串行 I/O 数：	1	端子数量：	208
片上数据RAM宽度：		最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	FQFP	封装形状：	SQUARE
封装形式：	FLATPACK, FINE PITCH	认证状态：	Not Qualified
RAM（字数）：	0	座面最大高度：	3.95 mm
最大压摆率：	400 mA	最大供电电压：	5.25 V
最小供电电压：	4.75 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	28 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, FDDI
Base Number Matches：	1

AM79C850KCW 数据手册

PRELIMINARY

Advanced

Micro

Am79C850

SUPERNET 3

Devices

DISTINCTIVE CHARACTERISTICS

■ Compliant with the ANSI X3T9.5/ISO 9314

■ ANSI-compliant TP-PMD Stream Cipher

specification

Scrambling/Descrambling

— 100 Mbps data rate

— Timed token-passing protocol

— Ring topology

■ Full duplex operation: 200 Mbps continuous

data rate

■ Supports both fiber optic and copper twisted-

pair media

■ Complete memory management

■ Diagnostic features

— Supports 256K bytes of local frame buffer

memory

— Built in Self Test (BIST) in Address Filter,

Physical Layer Controller with Scrambler

— Supports buffer memory bandwidths of

200 Mbps and 400 Mbps

■ Hardware Physical Connection Management

support

— Tag-Mode: minimum latency/highest

performance buffer memory management, ideal

for adapter card designs

■ Low power consumption—reduction of more

than 25% from SUPERNET 2 solution

FUNCTIONAL OVERVIEW

SUPERNET 3 FEATURES UPDATE

SUPERNET 3 is a 208-pin CMOS integration of FDDI

MAC, PHY, Address Filter, and clock generation and

recovery functions. It is the third generation FDDI

offering from AMD which integrates the SUPERNET 2

family of chips into a single-chip solution. Refer to the

SUPERNET 2 data book (PID 15502C) for basic

feature descriptions.

The basic feature description for SUPERNET 3 is

provided in the SUPERNET 2 data book. The enhanced

features are as listed below:

■ This is a CMOS integration of the redesigned

FORMAC Plus, an enhanced PLC, a 32-entry

address filter (AF, which is based on a Content

Addressable Memory, or CAM, core), and a CMOS

PDX core for clock and data recovery.

The SUPERNET 3 is backward compatible to the

SUPERNET 2 Tag Mode of operation in which the

SUPERNET 3 buffer memory interface logic maintains

the buffer memory as multiple FIFOs.

■ A 32-entry, extensible and fully maskable AF

allows additional individual and group addresses to

be supported.

The SUPERNET 3 provides DMA channels, arbitrates

access to the network buffer memory, and controls the

data path between the buffer memory and the medium.

The MAC also implements the timed-token protocol and

receive/transmit control as specified for the Media

Access Control (MAC) sublayer of the ISO standard

9314-2 for FDDI. The Physical Layer functions defined

by the ISO 9314-1 are performed by the SUPERNET 3.

■ The physical data transmitter and receiver (PDX)

circuits are also embedded on-chip using

proprietary digital clock-recovery technology.

■ For the purposes of implementing copper PMD,

the scrambler/descrambler functions are

embedded within the chip.

■ The Buffer Memory interface has been modified to

support slower SRAM’s (35 ns) without affecting

backward compatibility with SUPERNET 2.

SUPERNET

3 implements on-chip digital clock

recovery and transmit functions for fiber. To support

copper media, the PHY-PMD interface is maintained

and an external module can be implemented in

the same footprint as the fiber optic transceiver to

perform the MLT-3 encoding/decoding and equaliza-

tion. SUPERNET 3 integrates the scrambler and

descrambler functions for transmissions over

copper media.

■ SUPERNET 3 supports the FDDI single

attachment station (SAS) but is capable of

supporting a dual attachment station (DAS)

Publication# 19574 Rev. A Amendment/0

Issue Date: April 1995

This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended

to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.

12 3 4 5 6 7...97

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与AM79C850KCW相关器件

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AM79C864AKCW	AMD	获取价格	Physical Layer Controller With Scrambler (PLC-S)
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AM79C873KCW	AMD	获取价格	NetPHY⑩ -1 10/100 Mbps Ethernet Physical Laye
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