Datasheet > AM79C864AKCW

AM79C864AKCW

更新时间： 2024-10-29 04:32:31

品牌	Logo	应用领域
超微 - AMD		外围集成电路数据传输控制器时钟
页数	文件大小	规格书
51页	249K
描述
Physical Layer Controller With Scrambler (PLC-S)

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AM79C864AKCW 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	PLASTIC, QFP-120
针数：	120	Reach Compliance Code：	unknown
Is Samacsys：	N	地址总线宽度：	5
边界扫描：	NO	最大时钟频率：	12.5 MHz
最大数据传输速率：	12.5 MBps	外部数据总线宽度：	16
JESD-30 代码：	S-PQFP-G120	长度：	28 mm
低功率模式：	NO	串行 I/O 数：	1
端子数量：	120	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	QFP	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	3.95 mm
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	28 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, FDDI
Base Number Matches：	1

AM79C864AKCW 数据手册

PRELIMINARY

Advanced

Micro

Am79C864A

Physical Layer Controller With Scrambler (PLC-S)

Devices

DISTINCTIVE CHARACTERISTICS

■ Implements FDDI PHY layer protocol for

■ Line state detection

■ Repeat filter

ISO standard (FDDI) 9314-1

■ Implements ANSI standard Stream Cipher

■ Elasticity buffer and smoother functions

■ 4B/5B encoding/decoding

■ Full duplex operation

■ Data framing

Scrambling/Descrambling

■ Hardware Physical Connection Management

(PCM) support

■ Performs Physical Connection insertion and

■ Built-in Self Test

removal

■ On-chip Link Error Monitor (LEM) and Link

Confidence Test (LCT)

GENERAL DESCRIPTION

The Physical Layer Controller with Scrambler (PLC-S)

is a CMOS device which along with Physical Data

Transmitter (PDT) and Physical Data Receiver (PDR)

implements the Physical Layer Protocol (PHY) and por-

tions of the Station Management (SMT) of the ANSI Fi-

ber Distributed Data Interface (FDDI) standard. The

PLC-S, PDT and PDR are collectively known as the

AmPHY. PHY functions performed by the PLC-S in-

clude framing of data on symbol pair boundaries, the

elasticity buffer function, the smoothing function, 4B/5B

encoding and decoding of symbols, line state detection,

the repeat filter function, and Stream Cipher Scram-

bling/Descrambling. SMT functions performed include

Physical Connection Management (PCM), Physical

Connection insertion and removal and Link

Error Monitor.

The PLC-S receives byte-wide data from the MAC at

12.5 million bytes per second, encodes the data and

sends out symbol-wide data at 25 million symbols per

second to PDT chip. In the transmit path, there is a Re-

peat Filter to detect corrupted symbols and convert

them into the specified pattern of Halt and Idle symbols.

The Repeat Filter in each PLC-S chip converts the last

byte of a frame fragment into Idle symbols and thus

eventually removing fragments from the ring.

The PLC-S device includes a Stream Cipher Scrambler/

Descrambler as prescribed in the ANSI TP-PMD stan-

dard for transmission over twisted-pair cable. For

copper-based designs, the scrambler/descrambler may

be enabled either through software or hardware. For fi-

ber-based designs, the scrambler/descrambler is dis-

abled by default. For a detailed description of the

ANSI-compliant copper FDDI system using the PLC-S

device, refer to AMD PID #18258A, Implementing FDDI

over Copper; The ANSI X3T9.5 Standard.

The PLC-S chip receives symbol-wide (5 bits) data

along with a 25 MHz recovered clock from the PDR chip

and searches for a JK symbol pair (also known as Start-

ing Delimiter). It uses the starting delimiter to establish

byte boundaries (i.e. to frame the data).

ThePCMinitializestheconnectionofneighboringPHYs

and manages the PHY signaling. PCM consists of the

PCM state machine, which determines the timing and

state requirements for PCM, and the PCM Pseudo

Code, which provides the information to be communi-

cated to the neighboring PCM and specifies the connec-

tion policies. The PLC-S chip contains the PCM State

Machine, while the PCM Pseudo Code is controlled by

software. The PCM State Machine communicates with

other PCMs using a bit signaling mechanism whereby

certain line states are received and transmitted. The

PCM also makes use of the Link Error Monitor in the

Framed data is then sent to the Elasticity Buffer which

serves to compensate for the frequency difference be-

tween the recovered clock and the local clock. Data out-

put by the Elasticity Buffer is checked by the Smoother

and when necessary, Idle symbols are inserted be-

tween frames to maintain a minimum number of Idle

symbols in the interframe gap.

The data is then decoded and sent to the Media Access

Control (MAC) chip. The data is byte-wide (10 bits) and

is clocked by a 12.5 MHz local clock.

Publication# 15535 Rev. B Amendment/0

Issue Date: November 1993

This document contains information on a product under development at Advanced Micro Devices, Inc. The information

is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed

product without notice.

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